86 lines
3.1 KiB
Plaintext
86 lines
3.1 KiB
Plaintext
#
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# IP27 multi-processor product definitions.
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#
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# SN0 R10K with KONA
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#
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# Fundamental constants of the build tree (distinct from source tree).
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# They may be different for each product. Therefore if several products are
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# built from one source tree, that source tree should contain a commondefs
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# for each product.
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#
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SYSTEM = SVR4
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CPUBOARD= IP27
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COMPLEX = MP
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CPUARCH = R10000
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PRODDEFS=-DSN0
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GFXBOARD= KONA
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SUBGR = IP27
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KMODEOPT = -DDISCONTIG_PHYSMEM -DNUMA_BASE -DNUMA_PM \
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-DNUMA_TBORROW -DNUMA_MIGR_CONTROL \
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-DNUMA_REPLICATION -DNUMA_REPL_CONTROL -DNUMA_SCHED \
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-DLARGE_CPU_COUNT -DHUB2_NACK_WAR \
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-DBRIDGE_ERROR_INTR_WAR -DMAPPED_KERNEL \
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-DHUB_ERR_STS_WAR -DHUB_MIGR_WAR \
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-DFRU -DSN \
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-DSN0_USE_BTE -DBTE_BZERO_WAR -DREV1_BRIDGE_SUPPORTED \
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-DHUB_II_IFDR_WAR -DRTINT_WAR -DPCOUNT_WAR -DBRIDGE_B_DATACORR_WAR \
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-DIP27_CPU_EARLY_INIT_WAR=1
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SUBPRODUCT=
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LARGE_CPU_COUNT=1
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COMPILATION_MODEL=64
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IOC3_PIO_MODE=0
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# Turn on IPA build of stand tree
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COMPILATION_MODEL_SAOPT=IPA
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include $(RELEASEDEFS)
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#
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# Workaround definitions
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#
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# -DBRIDGE1_TIMEOUT_WAR - Adjust the arbitartion time to keep the
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# 1.0 bridge chip from corrupting data. Also disable
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# certain error interrupts.
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# -DBRIDGE_ERROR_INTR_WAR - We seem to get erroneous error interrupts
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# from the bridge. Disable BRIDGE_IMR_PCI_MST_TIMEOUT,
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# BRIDGE_ISR_RESP_XTLK_ERR, and BRIDGE_ISR_LLP_TX_RETRY
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# -DIP27_NIC_WAR - The numer in a can doesn't work on early IP27 boards.
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#
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# -sw, 5/28/96
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#
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# HUB_MIGR_WAR: The hub logic to generate a migration interrupt based
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# on the difference of home and remote reference counters
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# is not right. Probably it will be fixed in rev2.1.
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# The workaround provides an alternative by not using
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# the migration difference threshold register.
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#
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# HUB_ERR_STS_WAR: If any write errors happen when the hub error
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# registers are clear, we start losing WRB and subsequently
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# hang the CPU. This WAR ensures that the error status registers
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# have a RRB error in them.
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#
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# T5_WB_SURPRISE_WAR: The T5 incorrectly acknowledges a cache line
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# invalidate under some circumstances. It later proceeds to
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# writeback the cache line, resulting in a protocol error. This
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# will be fixed in T5 2.6, but in the meanwhile this WAR
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# attempts to detect if we ran into this problem.
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# Later, we should be able to kill user processes refrerencing
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# the page and let the system not panic.
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#
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# HUB_II_IFDR_WAR: The hub II IFDR fifo count gets incremented once
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# in a while and this can cause hangs and
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# corruption if not caught and fixed.
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#
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#
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# RTINT_WAR: the realtime interrupt on IOC3 is tied to the same interrupt as serial,
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# parallel and kbd/mouse, making it impossible to isolate the interrupt.
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# This makes it useless as a realtime interrupt. As a workaround we disable
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# interrupts to these other devices and poll them instead when RT interrupts
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# are in use.
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#
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#
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# PCOUNT_WAR: Under certain circumstances all the ICRBs can end up in DEX
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# mode. This will cause a system hang. This code will allow us to
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# spot the problem in the FRU Analyzer.
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#
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