113 lines
3.8 KiB
C
113 lines
3.8 KiB
C
/* selects cache(s) for alter. Note that
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* since the icache tests are separated, the BOTH option refers to
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* the primary data and (combined) secondary. */
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#define PRIMARYD 0
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#define PRIMARYI 1
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#define SECONDARY 2
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#define BOTH 3
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#define DO_MEMORY 4
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#define PHYS_CHECK_LO (PHYS_RAMBASE + 0x01400000)
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#define SR_FORCE_ON (SR_CU0 | SR_CU1 | SR_CE | SR_IEC)
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#define SR_FORCE_OFF (SR_CU0 | SR_CU1 | SR_IEC)
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#define SR_FORCE_NOERR (SR_CU0 | SR_CU1 | SR_CE | SR_DE )
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#define SR_NOERR (SR_CU0 | SR_CU1 | SR_DE )
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#ifndef LOCORE
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#include <sys/types.h>
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/* indicates which cache state to set.
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* Some are specific to primary or secondary. Note that DIRTY_EXCL in
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* primary sets the writeback bit therefore acting like the secondary
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* does in that state. The DIRTY_EXCL_NWB state applies only to the
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* primary and is the special case where a line is read from a dirty
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* secondary but not modified in the primary. */
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enum c_states {
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INVALIDL, /* P or S: cache line is invalid */
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CLEAN_EXCL, /* P or S: clean exclusive */
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DIRTY_EXCL, /* P or S: dirty exclusive */
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DIRTY_EXCL_NWB /* P: Dirty Excl. w/ writeback bit clear */
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};
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enum mem_space {
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k0seg, /* cached, unmapped access */
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k1seg, /* uncached, unmapped access */
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k2seg /* mapped; specified caching strategy */
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};
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/* get_tag rolls phys addrs from the taglo register to their correct
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* 31-bit positions before placing them in the tag_info.physaddr
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* field for easy comparision. The below masks return the valid portion
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* of the address (depending upon which cache the tag is from).
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*/
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#define PINFOADDRMASK 0xFFFFF000
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#define SINFOADDRMASK 0xFFFE0000
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/* top bit if phys addrs in taglo is 35: we want it to be 31 so roll left 4 */
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#define TAGADDRLROLL 4
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/* roll the 3 vindex (2ndary cache) bits from their taglo spot (9..7)
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* to their real positions (14..12) for easy comparision by get_tag_info */
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#define SVINDEXLROLL 5
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#define INFOVINDMASK 0x7000
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/* define bit-rolls to get cache-state portion to bottom of tag_lo word. */
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#define PSTATE_RROLL 6 /* tag_lo bits 7..6 indicate pcache state */
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#define SSTATE_RROLL 10 /* tag_lo bits 12..10 indicate scache state */
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/* several primitives return MISSED_2NDARY when a cache instruction on
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* an address doesn't hit the secondary cache */
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#define MISSED_2NDARY (-2)
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/* sbd.h contains the masks for accessing the primary and secondary
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* fields in the TagLo register. The below #defines manipulate
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* those values into positions in the tag_info struct and then mask
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* the valid parts of those fields for use by get_tag_info.
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*
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* The tag_info struct holds the state (in the low 2 or 3 bits depending
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* upon which cache is being queried), the 3 Vindex bits shifted to
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* their proper position for use (if the tag is from secondary cache),
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* and the upper bits of the physaddr, also shifted to their useable
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* positions. If the tag is from a primary line the tag reported bits
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* 35..12, so physaddr contains bits 31..12 of the physical address.
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* If it is a secondary line, the tag contained bits 35..17, so physaddr
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* will contain bits 31..17.
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*/
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typedef struct tag_info {
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ushort state;
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ushort vindex;
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uint physaddr;
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} tag_info_t;
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/* tag_regs structs hold the contents of the TagHi and TagLo registers,
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* which cache tag instructions use to read and write the primary and
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* secondary caches.
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*/
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typedef struct tag_regs {
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unsigned int tag_lo;
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unsigned int tag_hi;
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} tag_regs_t;
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extern int _sidcache_size;
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extern int _scache_linesize;
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extern int _scache_linemask;
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extern int _icache_size;
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extern int _icache_linesize;
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extern int _icache_linemask;
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extern int _dcache_size;
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extern int _dcache_linesize;
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extern int _dcache_linemask;
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int pd_HWBINV(uint *);
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#define PD_SIZE _dcache_size
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#define PDL_SIZE _dcache_linesize
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#define PI_SIZE _icache_size
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#define PIL_SIZE _icache_linesize
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#define SID_SIZE _sidcache_size
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#define SIDL_SIZE _scache_linesize
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#endif /* LOCORE */
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