73 lines
1.7 KiB
Groff
73 lines
1.7 KiB
Groff
'\"macro stdmacro
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.TH CACHECTL 2
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.SH NAME
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cachectl \- mark pages cacheable or uncacheable
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.SH SYNOPSIS
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.B "#include <sys/cachectl.h>"
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.sp
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.B "int cachectl (void \(**addr, int nbytes, int op);"
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.SH DESCRIPTION
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The
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.I cachectl
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system call allows a process to make ranges of its
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address space cacheable or uncacheable.
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Initially,
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a process's entire address space is cacheable.
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.PP
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The
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.I op
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parameter may be one of:
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.TP 17
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.B CACHEABLE
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Make the indicated pages cacheable
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.TP
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.B UNCACHEABLE
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Make the indicated pages uncacheable
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.PP
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The CACHEABLE and UNCACHEABLE \f2op\f1's affect the address range indicated
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by \f2addr\f1 and \f2nbytes\f1.
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.I addr
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must be page aligned and nbytes must be a multiple of the page size.
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.PP
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Changing a page from UNCACHEABLE state to CACHEABLE state will cause both the
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instruction and data caches to be flushed if necessary to avoid stale cache
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information.
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.PP
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On Power Indigo2, Indigo2 10000 and Power Challenge M systems,
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user programs are not allowed uncached access to main memory,
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so requesting this will fail with
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EINVAL.
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.PP
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On systems with hardware coherent caches,
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.I cachectl
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will complete successfully, but not actually allow memory to be accessed
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uncached.
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.SH "RETURN VALUE"
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.I cachectl
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returns 0 when no errors are detected.
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If errors are detected,
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.I cachectl
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returns \-1 with the error cause indicated in \f2errno\f1.
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.SH ERRORS
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.TP 17
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.SM [EINVAL]
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The
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.I op
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parameter is not one of CACHEABLE or UNCACHEABLE, or is UNCACHEABLE on
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a Power Indigo2, Indigo2 10000 or Power Challenge M.
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.TP
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.SM [EINVAL]
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The
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.I addr
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parameter is not page aligned,
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or
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.I nbytes
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is not a multiple of the page size.
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.TP
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.SM [EFAULT]
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Some or all of the address range
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.I addr
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to (\f2addr\f1+\f2nbytes\f1-1) is not accessible.
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.SH "SEE ALSO"
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cacheflush(2)
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