100 lines
2.8 KiB
C
100 lines
2.8 KiB
C
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#ifndef __IDE_phy_
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#define __IDE_phy_
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/*
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* Copyright 1995, Silicon Graphics, Inc.
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* ALL RIGHTS RESERVED
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*
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* UNPUBLISHED -- Rights reserved under the copyright laws of the United
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* States. Use of a copyright notice is precautionary only and does not
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* imply publication or disclosure.
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*
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* U.S. GOVERNMENT RESTRICTED RIGHTS LEGEND:
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* Use, duplication or disclosure by the Government is subject to restrictions
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* as set forth in FAR 52.227.19(c)(2) or subparagraph (c)(1)(ii) of the Rights
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* in Technical Data and Computer Software clause at DFARS 252.227-7013 and/or
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* in similar or successor clauses in the FAR, or the DOD or NASA FAR
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* Supplement. Contractor/manufacturer is Silicon Graphics, Inc.,
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* 2011 N. Shoreline Blvd. Mountain View, CA 94039-7311.
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*
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* THE CONTENT OF THIS WORK CONTAINS CONFIDENTIAL AND PROPRIETARY
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* INFORMATION OF SILICON GRAPHICS, INC. ANY DUPLICATION, MODIFICATION,
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* DISTRIBUTION, OR DISCLOSURE IN ANY FORM, IN WHOLE, OR IN PART, IS STRICTLY
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* PROHIBITED WITHOUT THE PRIOR EXPRESS WRITTEN PERMISSION OF SILICON
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* GRAPHICS, INC.
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*/
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#ident "ide/godzilla/include/d_phyregs.h: $Revision: 1.1 $"
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#define PHY_CONTROL 0x0
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#define PHY_STATUS 0x1
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#define PHY_ID1 0x2
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#define PHY_ID2 0x3
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#define PHY_AUTO_NEG_ADD 0x4
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#define PHY_AUTO_NEG_LINK_PTNR 0x5
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#define PHY_AUTO_NEG_EXP 0x6
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#define PHY_EXT_CONTROL 0x16
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#define PHY_QUICKPOLL_STATUS 0x17
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#define PHY_10BASET 0x18
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#define PHY_EXT_CONTROL2 0x19
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#define PHY_CONTROL_MASK 0xFFFF
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#define PHY_CONTROL_DEFAULT 0x0
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#define PHY_STATUS_MASK 0xFFFF
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#define PHY_STATUS_DEFAULT 0x0
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#define PHY_ID1_MASK 0xFFFF
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#define PHY_ID1_DEFAULT 0x15
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#define PHY_ID2_MASK 0xFFFF
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#define PHY_ID2_DEFAULT 0xF422
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#define PHY_AUTO_NEG_ADD_MASK 0xFFFF
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#define PHY_AUTO_NEG_ADD_DEFAULT 0x1e1
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#define PHY_AUTO_NEG_LINK_PTNR_MASK 0xFFFF
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#define PHY_AUTO_NEG_LINK_PTNR_DEFAULT 0x0
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#define PHY_AUTO_NEG_EXP_MASK 0xFFFF
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#define PHY_AUTO_NEG_EXP_DEFAULT 0x0
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#define PHY_EXT_CONTROL_MASK 0xFFFF
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#define PHY_EXT_CONTROL_DEFAULT 0x0
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#define PHY_QUICKPOLL_STATUS_MASK 0xFFFF
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#define PHY_QUICKPOLL_STATUS_DEFAULT 0x0
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#define PHY_10BASET_MASK 0x3F
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#define PHY_10BASET_DEFAULT 0x0
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#define PHY_EXT_CONTROL2_MASK 0xFFFF
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#define PHY_EXT_CONTROL2_DEFAULT 0x0
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#define PHY_BUSY 0x800
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#define PHY_ADDR 0x020
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#define PHY_READ 0x400
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#define PHY_WRITE 0x000
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typedef __uint32_t phyregisters_t;
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/*phy PCI configuration space*/
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#define PHY_AUTO_NEG_AD 0x4 ADD here:wq
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/*
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* constants used in phy_regs.c
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*/
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#define PHY_REGS_PATTERN_MAX 6
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typedef struct _phy_Registers {
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char *name; /* name of the register */
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__uint32_t address; /* address */
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__uint32_t mode; /* read / write only or read & write */
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__uint32_t mask; /* read-write mask */
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__uint32_t def; /* default value */
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} phy_Registers;
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#endif /* __IDE_phy_ */
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