51 lines
1.3 KiB
C
51 lines
1.3 KiB
C
#ident "$Revision: 1.10 $"
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#ifndef __ML_H__
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#define __ML_H__ 1
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#include "sys/asm.h"
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#include "sys/regdef.h"
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#if (_MIPS_SIM == _ABI64 || _MIPS_SIM == _ABIN32)
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#define lreg ld
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#define sreg sd
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#define BPREG 8
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#else
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#define lreg lw
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#define sreg sw
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#define BPREG 4
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#endif
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#if R4000 && (defined(IP22) || defined(IP19))
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/*
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* Some 250MHz R4K modules will flip bits in the entrylo0 and
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* entrylo1 registers when written, when there's a certain bit
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* pattern in the register already, the workaround is to make
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* sure a zero exists before the value is written.
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*/
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#define TLBLO_FIX_250MHz(entrylo) mtc0 zero, entrylo
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#else
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#define TLBLO_FIX_250MHz(entrylo)
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#endif /* R4000 && (IP22 || IP19) */
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#endif
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#ifdef IP28 /* see irix/kern/ml/ml.h for the gory details */
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#define CACHE_BARRIER_AT(o,r) \
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cache CACH_BARRIER,o(r)
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#define ORD_CACHE_BARRIER_AT(o,r) \
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.set noreorder; CACHE_BARRIER_AT(o,r); .set reorder
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#define CACHE_BARRIER_SP \
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CACHE_BARRIER_AT(0,sp)
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#define CACHE_BARRIER CACHE_BARRIER_SP
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#define AUTO_CACHE_BARRIERS_DISABLE .set no_spec_mem
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#define AUTO_CACHE_BARRIERS_ENABLE .set spec_mem
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#else
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#define CACHE_BARRIER_AT(o,r)
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#define ORD_CACHE_BARRIER_AT(o,r)
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#define CACHE_BARRIER_SP
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#define CACHE_BARRIER
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#define AUTO_CACHE_BARRIERS_DISABLE
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#define AUTO_CACHE_BARRIERS_ENABLE
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#endif /* IP28 */
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