50 lines
863 B
ArmAsm
50 lines
863 B
ArmAsm
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#if _MIPS_SIM != _ABI64
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#define R4000 1
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#define _PAGESZ 4096
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#define IP20 1
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#include "ml.h"
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#include <regdef.h>
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#include <sys/cpu.h>
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#include <sys/loaddrs.h>
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#include <sys/sbd.h>
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#include <asm.h>
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#define SCACHE_SIZE 0x100000
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#define SCACHE_LINESIZE (32*4)
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#define SCACHE_LINEMASK ((32*4)-1)
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#define MIN_CACH_POW2 12
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LEAF(ip20promhack_cacheflush)
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.set noreorder
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LI t0,K0_RAMBASE
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LI t3,SCACHE_SIZE
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addu t3,t0
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and t0,~SCACHE_LINEMASK
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1:
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lw zero,(t0) # read from line to flush
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#define COMPANION_BIT 0x00400000
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li t1,COMPANION_BIT # generate companion
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xor t1,t0
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li t2,K0_RAMBASE
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bgeu t1,t2,2f
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nop
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or t1,K0_RAMBASE
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2:
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lw zero,(t1) # cause writeback
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cache CACH_SD|C_HINV,0(t1) # invalidate cache line
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.set reorder
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addu t0,SCACHE_LINESIZE
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bltu t0,t3,1b
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j ra
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END(ip20promhack_cacheflush)
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#endif
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