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38 lines
1014 B
Plaintext
38 lines
1014 B
Plaintext
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Sources
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-------
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Timing and the idea for the voltage divider is from:
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http://faculty.lasierra.edu/~ehwang/public/mypublications/VGA Monitor Controller.pdf
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More timing parameters:
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http://tinyvga.com/vga-timing/640x480@60Hz
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Signal 8:10 VGA
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------- ------- ---
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R DAT2 1
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VSYNC DAT3 14
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HSYNC CMD 13
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G DAT0 2
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B DAT1 3
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GND GND 5
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http://en.wikipedia.org/wiki/VGA_connector
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Timing
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------
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Since the Ingenic CPUs take about 8.5 PCLK cycles for a GPIO set or clear,
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and we can only set or clear a set of signals in GPIO operation, but not
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set some and clear others, we cannot have a real 320 horizontal pixels.
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Instead, set and clear operations alternate. This means that the best-case
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resolution is equivalent to 320 pixels (if the original pixel boundaries
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coincide with the set/clear phases), but it can be as low as 160 pixels if
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the boundaries don't match.
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Furthermore, timing is still a bit too tight. We therefore use a pixel
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clock that's about 10% slower than the original. Luckily, most monitors
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don't mind.
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