mirror of
git://projects.qi-hardware.com/ben-blinkenlights.git
synced 2024-07-01 00:27:37 +03:00
957491d209
- regs4740.h: macros to access selected Jz4740 registers - ubb-vga2.c: replaced all pointers to registers with access macros - ubb-vga2.c (line_cycles): we now seem to be 0.1 us slower
64 lines
2.3 KiB
C
64 lines
2.3 KiB
C
/*
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* regs4740.h - Jz4740 register definitions (subset)
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*
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* Written 2011 by Werner Almesberger
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* Copyright 2011 Werner Almesberger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef REGS4740_H
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#define REGS4740_H
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#include <stdint.h>
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#define SOC_BASE 0x10000000
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#define REG(n) (*(volatile uint32_t *) ((REG_BASE_PTR)+(n)))
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#define CGU(n) REG(0x00000+(n))
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#define INTC(n) REG(0x01000+(n))
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#define TCU(n) REG(0x02000+(n))
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#define GPIO(n) REG(0x10000+(n))
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#define MSC(n) REG(0x21000+(n))
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#define CLKGR CGU(0x0020) /* Clock Gate */
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#define MSCCDR CGU(0x0068) /* MSC device clock divider */
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#define PDPIN GPIO(0x300) /* port D pin level */
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#define PDDATS GPIO(0x314) /* port D data set */
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#define PDDATC GPIO(0x318) /* port D data clear */
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#define PDFUNS GPIO(0x344) /* port D function set */
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#define PDFUNC GPIO(0x348) /* port D function clear */
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#define PDDIRS GPIO(0x364) /* port D direction set */
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#define PDDIRC GPIO(0x368) /* port D direction clear */
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#define ICMR INTC(0x04) /* Interrupt controller mask */
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#define ICMSR INTC(0x08) /* Interrupt controller mask set */
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#define ICMCR INTC(0x0c) /* Interrupt controller mask clear */
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#define TSSR TCU(0x2c) /* Timer STOP set */
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#define TSCR TCU(0x3c) /* Timer STOP clear */
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#define TESR TCU(0x14) /* Timer counter enable set */
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#define TECR TCU(0x18) /* Timer counter enable clear */
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#define TCSR(n) TCU(0x4c+0x10*(n)) /* Timer control */
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#define TDFR(n) TCU(0x40+0x10*(n)) /* Timer data full */
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#define TCNT(n) TCU(0x48+0x10*(n)) /* Timer counter */
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#define MSC_STRPCL MSC(0x00) /* Start/stop MMC/SD clock */
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#define MSC_STAT MSC(0x04) /* MSC status */
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#define MSC_CLKRT MSC(0x08) /* MSC clock rate */
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#define MSC_CMDAT MSC(0x0c) /* MMC/SD command and data control */
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#define MSC_RESTO MSC(0x10) /* MMC/SD response time out */
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#define MSC_BLKLEN MSC(0x18) /* MMC/SD block length */
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#define MSC_NOP MSC(0x1c) /* MMC/SD number of blocks */
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#define MSC_CMD MSC(0x2c) /* MMC/SD command index */
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#define MSC_ARG MSC(0x30) /* MMC/SD command argument */
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#define MSC_TXFIFO MSC(0x3c) /* MMC/SD transmit data FIFO */
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#endif /* !REGS4740_H */
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