ben-wpan/atusd/ERRATA

Version 20100903:

- changed C7 to 1 nF to debug a signal attenuation problem. Turned out to be
  a bad trace. According to simulations, 22 pF should be more than enough.

- added wire connecting uSD-side ground plane to ground plane at outer edge,
  to improve CLK signal return. (Probably unnecessary, too.)

- the footprint of the transistor (Q1) is reversed :-( It works after
  converting the chip from SOT to PLCC.

- not an erratum, but with experiments showing power-on reset to be
  reliable, we can consider removing the hardware reset circuit. This will
  also simplify the layout.

Version 20100908:

- SPI activity causes the PLL to unlock. Specifically, toggling nSEL does
  this.

- work-around on second 20100908 board: replace the resistive divider with
  a capacitative divider. See sim/cdiv.sch. This is a simple BOM change:

  C7 -> 0 R
  R3 -> 33 pF
  R4 -> 220 pF

  Applied work-around also to first 20100908 board after confirming dismal
  performance caused by clock instability.

- considering that the clock input has a Vpp of only 400-500 mV, we should
  have a ground plane also under as much of the the clock circuit as
  possible.

- via between pins 1 and 32 is too close to the chip for DIY PCBs

Version 20100912:

- zone fill did not reach upper GND end of antenna. This was not intended,
  but may be harmless or even an improvement.
New atusd errata and a few small CAM updates. - atusd/ERRATA: added errata section for version 20100908 - atusd/cam/doit: increase tool clearance from 1.5 mm to 2 mm - atusd/cam/pcb.pl (cut): cutting counter-clockwise did not reduce burr. Removed reversal of cutting direction. - atusd/cam/pcb.pl: made area selection formulas easier to understand 2010-09-09 15:23:18 +03:00			`Version 20100903:`

First part of the board bringup: power and clock. - atusd/ERRATA: variations of the circuit being debugged from the design - tools/Makefile, tools/try.c, tools/lib/atusd.c: user-space tool to enable the board and (in the future) establish communication - atusd/sim/clk.sch: simulation of CLK attenuation circuit with capacitative load from scope probe 2010-09-05 05:14:57 +03:00			`- changed C7 to 1 nF to debug a signal attenuation problem. Turned out to be`
			`a bad trace. According to simulations, 22 pF should be more than enough.`

			`- added wire connecting uSD-side ground plane to ground plane at outer edge,`
			`to improve CLK signal return. (Probably unnecessary, too.)`
Next part of board bringup: reset and power cycling. - atusd/ERRATA: one more problem: the transistor footprint is wrong - atusd/tools/lib/atusd.c (atusd_cycle, atusd_reset): added power cycling and hardware reset - atusd/tools/lib/atusd.h: be nice and make a header file - atusd/tools/try.c: be nice and use header files (caught a bug as well) 2010-09-05 20:07:01 +03:00
			`- the footprint of the transistor (Q1) is reversed :-( It works after`
			`converting the chip from SOT to PLCC.`
Board bringup: talk to the chip and read IDs. - atusd/ERRATA: mention that the reset circuit can go, as expected - atusd/tools/Makefile: add include path to at86rf230.h - atusd/tools/lib/atusd.c: include atusd.h, for consistency checking - atusd/tools/lib/atusd.c (spi_begin, spi_end, spi_data_in, spi_data_out, spi_send_partial, spi_recv, spi_finish, spi_send): low-level functions to access our modified SPI - atusd/tools/lib/atusd.h, atusd/tools/lib/atusd.c (atusd_reg_write, atusd_reg_read): register read and write access - atusd/tools/try.c: read and print chip IDs 2010-09-05 22:59:59 +03:00
			`- not an erratum, but with experiments showing power-on reset to be`
			`reliable, we can consider removing the hardware reset circuit. This will`
			`also simplify the layout.`
New atusd errata and a few small CAM updates. - atusd/ERRATA: added errata section for version 20100908 - atusd/cam/doit: increase tool clearance from 1.5 mm to 2 mm - atusd/cam/pcb.pl (cut): cutting counter-clockwise did not reduce burr. Removed reversal of cutting direction. - atusd/cam/pcb.pl: made area selection formulas easier to understand 2010-09-09 15:23:18 +03:00
			`Version 20100908:`

			`- SPI activity causes the PLL to unlock. Specifically, toggling nSEL does`
			`this.`
Improved clock stability by using a capacitative divider and found more minor issues. - atusd/ERRATA: work around the clock instability by replacing the resistive divider with a capacitative divider - atusd/ERRATA: a ground plane under the clock circuit would also be good to have - atusd/ERRATA: via near pin 1 is too close to the chip if we need to cut wires (in DIY boards) - atusd/sim/cdiv.sch: simulation of the capacitative divider 2010-09-09 18:35:47 +03:00
			`- work-around on second 20100908 board: replace the resistive divider with`
			`a capacitative divider. See sim/cdiv.sch. This is a simple BOM change:`

			`C7 -> 0 R`
			`R3 -> 33 pF`
			`R4 -> 220 pF`

Performance comparison of atusb vs. atusd. - atusd/tests/send-20100909: conducted performance comparison of atusb vs. atusd - atusd/ERRATA: changed also first board to capacitative divider 2010-09-10 02:38:50 +03:00			`Applied work-around also to first 20100908 board after confirming dismal`
			`performance caused by clock instability.`

Improved clock stability by using a capacitative divider and found more minor issues. - atusd/ERRATA: work around the clock instability by replacing the resistive divider with a capacitative divider - atusd/ERRATA: a ground plane under the clock circuit would also be good to have - atusd/ERRATA: via near pin 1 is too close to the chip if we need to cut wires (in DIY boards) - atusd/sim/cdiv.sch: simulation of the capacitative divider 2010-09-09 18:35:47 +03:00			`- considering that the clock input has a Vpp of only 400-500 mV, we should`
			`have a ground plane also under as much of the the clock circuit as`
			`possible.`

			`- via between pins 1 and 32 is too close to the chip for DIY PCBs`
atusd/ERRATA: started errata section for 100912. Nothing major so far. 2010-09-14 19:44:16 +03:00
			`Version 20100912:`

			`- zone fill did not reach upper GND end of antenna. This was not intended,`
			`but may be harmless or even an improvement.`