2010-09-09 15:23:18 +03:00
|
|
|
Version 20100903:
|
|
|
|
|
|
2010-09-05 05:14:57 +03:00
|
|
|
- changed C7 to 1 nF to debug a signal attenuation problem. Turned out to be
|
|
|
|
|
a bad trace. According to simulations, 22 pF should be more than enough.
|
|
|
|
|
|
|
|
|
|
- added wire connecting uSD-side ground plane to ground plane at outer edge,
|
|
|
|
|
to improve CLK signal return. (Probably unnecessary, too.)
|
2010-09-05 20:07:01 +03:00
|
|
|
|
|
|
|
|
- the footprint of the transistor (Q1) is reversed :-( It works after
|
|
|
|
|
converting the chip from SOT to PLCC.
|
Board bringup: talk to the chip and read IDs.
- atusd/ERRATA: mention that the reset circuit can go, as expected
- atusd/tools/Makefile: add include path to at86rf230.h
- atusd/tools/lib/atusd.c: include atusd.h, for consistency checking
- atusd/tools/lib/atusd.c (spi_begin, spi_end, spi_data_in, spi_data_out,
spi_send_partial, spi_recv, spi_finish, spi_send): low-level functions
to access our modified SPI
- atusd/tools/lib/atusd.h, atusd/tools/lib/atusd.c (atusd_reg_write,
atusd_reg_read): register read and write access
- atusd/tools/try.c: read and print chip IDs
2010-09-05 22:59:59 +03:00
|
|
|
|
|
|
|
|
- not an erratum, but with experiments showing power-on reset to be
|
|
|
|
|
reliable, we can consider removing the hardware reset circuit. This will
|
|
|
|
|
also simplify the layout.
|
2010-09-09 15:23:18 +03:00
|
|
|
|
|
|
|
|
Version 20100908:
|
|
|
|
|
|
|
|
|
|
- SPI activity causes the PLL to unlock. Specifically, toggling nSEL does
|
|
|
|
|
this.
|
