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git://projects.qi-hardware.com/ben-wpan.git
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atusb/fw/include/at86rf230.h: make one section per register, not one per field
Looked too confusing.
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@ -85,16 +85,11 @@ enum {
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REG_CONT_TX_1 = 0x3d,
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};
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/* --- TRX_STATUS [7] ------------------------------------------------------ */
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/* --- TRX_STATUS --- ------------------------------------------------------ */
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#define CCA_DONE (1 << 7)
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/* --- TRX_STATUS [6] ------------------------------------------------------ */
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#define CCA_STATUS (1 << 6)
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/* --- TRX_STATUS [4:0] ---------------------------------------------------- */
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#define TRX_STATUS_SHIFT 0
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#define TRX_STATUS_MASK 0x1f
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@ -116,7 +111,7 @@ enum {
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TRX_STATUS_TRANSITION = 0x1f /* ..._IN_PROGRESS */
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};
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/* --- TRX_STATE [7:5] ----------------------------------------------------- */
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/* --- TRX_STATE ----------------------------------------------------------- */
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#define TRAC_STATUS_SHIFT 5
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#define TRAC_STATUS_MASK 7
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@ -130,8 +125,6 @@ enum {
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TRAC_STATUS_INVALID = 7
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};
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/* --- TRX_STATE [4:0] ----------------------------------------------------- */
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#define TRX_CMD_SHIFT 0
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#define TRX_CMD_MASK 7
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@ -147,7 +140,7 @@ enum {
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TRX_CMD_TX_ARET_ON = 0x19,
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};
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/* --- TRX_CTRL_0 [7:6] ---------------------------------------------------- */
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/* --- TRX_CTRL_0 ---------------------------------------------------------- */
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#define PAD_IO_SHIFT 6
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#define PAD_IO_MASK 3
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@ -159,8 +152,6 @@ enum {
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PAD_IO_8mA
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};
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/* --- TRX_CTRL_0 [5:4] ---------------------------------------------------- */
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#define PAD_IO_CLKM_SHIFT 4
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#define PAD_IO_CLKM_MASK 3
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@ -171,12 +162,8 @@ enum {
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PAD_IO_CLKM_8mA,
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};
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/* --- TRX_CTRL_0 [3] ------------------------------------------------------ */
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#define CLKM_SHA_SEL (1 << 3)
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/* --- TRX_CTRL_0 [2:0] ---------------------------------------------------- */
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#define CLKM_CTRL_SHIFT 0
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#define CLKM_CTRL_MASK 3
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@ -208,39 +195,31 @@ enum {
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#define IRQ_MASK_MODE (1 << 1)
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#define IRQ_POLARITY (1 << 0)
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/* --- PHY_TX_PWR [7] ------------------------------------------------------ */
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/* --- PHY_TX_PWR -====----------------------------------------------------- */
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#define TX_AUTO_CRC_ON (1 << 7) /* 230 */
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/* --- PHY_TX_PWR [3:0] ---------------------------------------------------- */
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#define TX_PWR_SHIFT 0
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#define TX_PWR_MASK 0x0f
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/* --- PHY_RSSI [7] -------------------------------------------------------- */
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/* --- PHY_RSSI ------------------------------------------------------------ */
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#define RX_CRC_VALID (1 << 7)
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/* --- PHY_RSSI [4:0] ------------------------------------------------------ */
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#define RSSI_SHIFT 0
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#define RSSI_MASK 0x1f
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/* --- PHY_CC_CCA [7] ------------------------------------------------------ */
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/* --- PHY_CC_CCA ---------------------------------------------------------- */
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#define CCA_REQUEST (1 << 7)
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/* --- PHY_CC_CCA [6:5] ---------------------------------------------------- */
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#define CCA_MODE_SHIFT 5
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#define CCA_MODE_MASK 3
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/* --- PHY_CC_CCA [4:0] ---------------------------------------------------- */
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#define CHANNEL_SHIFT 0
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#define CHANNEL_MASK 0x1f
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/* --- CCA_THRES [3:0] ----------------------------------------------------- */
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/* --- CCA_THRES ----------------------------------------------------------- */
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#define CCA_ED_THRES_SHIFT 0
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#define CCA_ED_THRES_MASK 0x0f
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@ -256,24 +235,22 @@ enum {
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IRQ_BAT_LOW = 1 << 7
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};
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/* --- VREG_CTRL [7, 6, 3, 2] ---------------------------------------------- */
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/* --- VREG_CTRL ----------------------------------------------------------- */
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#define AVREG_EXT (1 << 7)
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#define AVDD_OK (1 << 6)
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#define DVREG_EXT (1 << 3)
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#define DVDD_OK (1 << 2)
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/* --- BATMON [5, 4] ------------------------------------------------------- */
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/* --- BATMON -------------------------------------------------------------- */
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#define BATMON_OK (1 << 5)
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#define BATMON_HR (1 << 4)
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/* --- BATMON [3:0] -------------------------------------------------------- */
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#define NATMON_VTH_SHIFT 0
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#define NATMON_VTH_MASK 0x0f
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/* --- XOSC_CTRL [7:4] ----------------------------------------------------- */
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/* --- XOSC_CTRL ----------------------------------------------------------- */
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#define XTAL_MODE_SHIFT 4
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#define XTAL_MODE_MASK 0x0f
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@ -284,49 +261,42 @@ enum {
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XTAL_MODE_INT = 0xf /* reset default */
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};
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/* --- XOSC_CTRL [3:1] ----------------------------------------------------- */
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#define XTAL_TRIM_SHIFT 4
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#define XTAL_TRIM_MASK 0x0f
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/* --- XAH_CTRL [7:4] ------------------------------------------------------ */
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/* --- XAH_CTRL ------------------------------------------------------------ */
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#define MAX_FRAME_RETRIES_SHIFT 4
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#define MAX_FRAME_RETRIES_MASK 0x0f
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#define MAX_CSMA_RETRIES_SHIFT 1
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#define MAX_CSMA_RETRIES_MASK 0x07
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/* --- PLL_CF [7] ---------------------------------------------------------- */
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/* --- PLL_CF -------------------------------------------------------------- */
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#define PLL_CF_START (1 << 7)
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/* --- PLL_DCU [8] --------------------------------------------------------- */
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/* --- PLL_DCU ------------------------------------------------------------- */
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#define PLL_DCU_START (1 << 7)
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/* --- CSMA_SEED_1 [7:6] --------------------------------------------------- */
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/* --- CSMA_SEED_1 --------------------------------------------------------- */
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#define MIN_BE_SHIFT 6
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#define MIN_BE_MASK 3
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/* --- CSMA_SEED_1 [5] ----------------------------------------------------- */
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#define AACK_SET_PD (1 << 5)
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/* --- CSMA_SEED_1 [3] ----------------------------------------------------- */
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#define I_AM_COORD (1 << 3)
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/* --- CSMA_SEED_1 [2:0] --------------------------------------------------- */
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#define CSMA_SEED_1_SHIFT 0
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#define CSMA_SEED_1_MASK 7
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/* --- REG_CONT_TX_0 [7:0] ------------------------------------------------- */
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/* --- REG_CONT_TX_0 ------------------------------------------------------- */
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#define CONT_TX_MAGIC 0x0f
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/* --- REG_CONT_TX_1 [7:0] ------------------------------------------------- */
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/* --- REG_CONT_TX_1 ------------------------------------------------------- */
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#define CONT_TX_MOD 0x00 /* modulated */
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#define CONT_TX_M2M 0x10 /* f_CH-2 MHz */
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