- atrf-txrx.c (tx_pwr, tx_pwr_230, tx_pwr_231, set_power): table of power
values depends on chip
- atrf-txrx.c (set_power): location of TX_AUTO_CRC_ON and use of
REG_PHY_TX_PWR depends on chip
- tools/lib/atrf.h, tools/lib/atrf.c (atrf_identify): added chip
identification function to library
- tools/atrf-id/atrf-id.c (show_info): print information returned by
atrf_identify
- tools/atrf-id/atrf-id.c (show_info): decode JEDEC manufacturer ID
- atusd.brd: moved antenna by 20 mil to make more room for vias
- atusd.brd: increased RF via density to up to 50-60 mil per via
- atusd.brd: increased zone clearance to 10 mil, to make board easier to
solder
- atusd.pro: changed ../components/at86rf230 to ../components/at86rf231
- atusd.sch (U1): set to AT86RF231
- atusd.sch: moved clock input from pin 29 to pin 28 (still XTAL1)
- atusd.sch: changed version to 20110104
- atrf.sch: replaced the AT86RF230 with the AT86RF231
- atusb.sch, usb.sch, atrf.sch: removed TST signal
- atrf.sch: grounded former TST pin
- atusb.brd: updated for TST removal
- atusb.brd: increased space between SLP_TR and nRST_RF vias
- atusb.brd: connect U2 pin 6 to ground pad
- atusb.sch, usb.sch, atrf.sch, atusb.brd: changed version to 20110104
- BOOKSHELF (at86rf231): the AT86RF231, successor of the AT86RF230
- BOOKSHELF (avt2027, aes): the AT86RF231's AES module
- BOOKSHELF: moved the aliases "transceiver", "txrx", and "atrf" from the
AT86RF230 to the AT86RF231
- BOOKSHELF: added aliases "rf230" and "rf231" for the transceivers
- bom/atrf.equ, bom/dk/digi-key.equ: added the AT86RF231(-ZU)
- atusb.brd: increased RF ground zone by 150 mil in an attempt to reduce
interferences between the the antenna and the rest of the circuit
- atusb.brd: added more vias around and inside the RF ground zone
- atusb.brd: set version to 20110102
Traces leaving a pad on the side may invite solder bridges to "false pads"
exposed at the edges of the chip, with unknown consequences.
- atusb.brd: make trace from P0.0 (IRQ_RF) leave pad at the front, not
at the side
- atusb.brd: make trave from P0.7 (SCLK) leave pad at front, not at the
side
- atusb.brd: nRST may need an external pull-up to VDD. Added via to bring
nRST and VDD within reach (pull-up suggested by Joerg Reisenweber)
- atusb.brd: increased version to 20101229
- atusb.brd: increase clearance between RF clock front ground area and MCU
(ground area acted as solder trap)
- atusb.brd: route nRST_RF trace out of corner (to avoid accidental
contact)
- atusb.brd: don't route VBUS corner trace underneat chip (for general
tidiness)
- atusb.brd: bumped version to 20101219
- atusb.brd: reduced RF front ground area to avoid interconnections very
close to the chip
- atusb.brd: reduced RF power front ground area to avoid interconnections
very close to the chip
- atusb.brd: moved via next to TXRX pad 18 (GND) to make room for making
CLK trace leave the pad at its end, not at its side
- atusb.brd: bumped design date to 20101217
