issues.
- atusd/ERRATA: work around the clock instability by replacing the
resistive divider with a capacitative divider
- atusd/ERRATA: a ground plane under the clock circuit would also be good to
have
- atusd/ERRATA: via near pin 1 is too close to the chip if we need to cut
wires (in DIY boards)
- atusd/sim/cdiv.sch: simulation of the capacitative divider
- atusd/ERRATA: added errata section for version 20100908
- atusd/cam/doit: increase tool clearance from 1.5 mm to 2 mm
- atusd/cam/pcb.pl (cut): cutting counter-clockwise did not reduce burr.
Removed reversal of cutting direction.
- atusd/cam/pcb.pl: made area selection formulas easier to understand
- atusd/ERRATA: one more problem: the transistor footprint is wrong
- atusd/tools/lib/atusd.c (atusd_cycle, atusd_reset): added power cycling and
hardware reset
- atusd/tools/lib/atusd.h: be nice and make a header file
- atusd/tools/try.c: be nice and use header files (caught a bug as well)
- atusd/ERRATA: variations of the circuit being debugged from the design
- tools/Makefile, tools/try.c, tools/lib/atusd.c: user-space tool to enable
the board and (in the future) establish communication
- atusd/sim/clk.sch: simulation of CLK attenuation circuit with capacitative
load from scope probe