mirror of
git://projects.qi-hardware.com/iris.git
synced 2024-12-28 12:49:54 +02:00
Add unbricking method
This commit is contained in:
Bas Wijnen
parent
5f9fd7cc0f
commit
9aff93c300
1
.gitignore
vendored
1
.gitignore
vendored
@ -23,3 +23,4 @@ mips/nanonote/server/missing
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mips/nanonote/server/usb-server
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fs/
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iris-sd.tar
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unbrick
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@ -320,4 +320,4 @@ static void erase (unsigned a):
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addr (row >> 8)
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addr (row >> 16)
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cmd (CMD_ERASE2)
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debug ("nand erase %d done\n", a)
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//debug ("nand erase %d done\n", a)
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@ -17,16 +17,20 @@
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start_load = 0x80600000
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load = 0x80000000
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UDC_BOOT = comment this out for sd boot
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# Uncomment one of these to select the boot method for the image.
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#UDC_BOOT = yes
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#SD_BOOT = yes
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UNBRICK = yes
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arch_iris_sources = mips/interrupts.cc mips/arch.cc
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boot_sources = mips/init.cc mips/nanonote/board.cc
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arch_headers = mips/arch.hh mips/nanonote/jz4740.hh mips/nanonote/board.hh mips/nand.hh
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udc_boot_programs = udc
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sd_boot_programs = sd+mmc partition fat
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unbrick_boot_programs = nand usb-mass-storage
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standard_boot_programs = bootinit
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programs = init usb-mass-storage gpio lcd bsquare ball buzzer metronome elfrun alarm rtc gui nand test boot booter $(udc_boot_programs) $(sd_boot_programs) $(standard_boot_programs)
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programs = init gpio lcd bsquare ball buzzer metronome elfrun alarm rtc gui test boot booter $(udc_boot_programs) $(sd_boot_programs) $(unbrick_boot_programs) $(standard_boot_programs)
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ARCH_CPPFLAGS = -I. -Imips -Imips/nanonote -Wa,-mips32 -DNANONOTE -DUSE_SERIAL
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CROSS = mipsel-linux-gnu-
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@ -34,21 +38,35 @@ OBJDUMP = $(CROSS)objdump
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junk = mdebug.abi32 reginfo comment pdr
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OBJCOPYFLAGS = $(addprefix --remove-section=.,$(junk))
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ifdef UDC_BOOT
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ifneq ($(UDC_BOOT),)
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boot_threads = $(standard_boot_programs) $(udc_boot_programs)
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threadlist = mips/nanonote/threadlist-udc
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ARCH_CXXFLAGS = -DNUM_THREADS=2
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BOOT_CPPFLAGS = -DUDCBOOT
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all: mips/nanonote/nand-boot.raw test
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mips/start.o: TARGET =
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else
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ifneq ($(SD_BOOT),)
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boot_threads = $(standard_boot_programs) $(sd_boot_programs)
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threadlist = mips/nanonote/threadlist-sd
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ARCH_CXXFLAGS = -DNUM_THREADS=4
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BOOT_CPPFLAGS = -DSDBOOT
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all: mips/nanonote/nand-boot.raw iris-sd.tar
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mips/start.o: TARGET = -DWRAPPED
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iris-sd.tar: $(addprefix fs/,$(addsuffix .elf,$(programs))) mips/start.raw.gz fs/init.config
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mkimage -A mips -T kernel -a $(start_load) -e $(shell /bin/sh -c '$(OBJDUMP) -t mips/start.elf | grep __start$$ | cut -b1-8') -n Iris -d mips/start.raw.gz fs/uimage | sed -e 's/:/;/g'
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cd fs && tar cvf ../$@ uimage init.config $(addsuffix .elf,$(programs)) --dereference
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else
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ifneq ($(UNBRICK),)
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boot_threads = $(standard_boot_programs) $(unbrick_boot_programs)
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ARCH_CXXFLAGS = -DNUM_THREADS=3
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BOOT_CPPFLAGS = -DUNBRICK
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all: mips/nanonote/nand-boot.raw iris.raw unbrick
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mips/start.o: TARGET =
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unbrick: mips/nanonote/unbrick.cc
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g++ -Wall -Wextra -Werror `pkg-config --cflags --libs shevek` -lusb $< -o $@
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else
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error Please define your boot method.
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endif
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endif
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endif
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iris.elf: LDFLAGS = --omagic -Ttext $(load)
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@ -83,7 +101,7 @@ nanonote-boot: mips/nanonote/nanonote-boot.cc mips/nanonote/sdram-setup.raw
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mips/nanonote/sdram-setup.elf: mips/nanonote/sdram-setup.ld
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mips/nanonote/sdram-setup.elf: LDFLAGS = --omagic -T mips/nanonote/sdram-setup.ld
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$(threadlist).o: $(addprefix fs/,$(addsuffix .elf,$(boot_threads)))
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mips/nanonote/threadlist.o: $(addprefix fs/,$(addsuffix .elf,$(boot_threads)))
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mips/boot.o: TARGET_FLAGS = -DMEMORY_SIZE="32 << 20"
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mips/init.o: TARGET_FLAGS = -I/usr/include
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source/bootinit.o: TARGET_FLAGS = -I/usr/include
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@ -99,10 +117,10 @@ source/charset.data: source/charset
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$< > $@
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%.o:%.S Makefile Makefile.arch mips/arch.hh
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$(CC) $(CPPFLAGS) $(TARGET_FLAGS) -DKERNEL_STACK_SIZE=0x1000 -c $< -o $@
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$(CC) $(CPPFLAGS) $(BOOT_CPPFLAGS) $(TARGET_FLAGS) -DKERNEL_STACK_SIZE=0x1000 -c $< -o $@
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# entry.o must be the first file. threadlist.o must be the first of the init objects (which can be freed after loading).
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iris.elf: mips/entry.o $(subst .cc,.o,$(iris_sources)) $(threadlist).o mips/boot.o $(subst .cc,.o,$(boot_sources))
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iris.elf: mips/entry.o $(subst .cc,.o,$(iris_sources)) mips/nanonote/threadlist.o mips/boot.o $(subst .cc,.o,$(boot_sources))
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$(LD) $(LDFLAGS) $^ -o $@
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mips/start.elf: mips/start.o
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@ -1,39 +0,0 @@
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// Iris: micro-kernel for a capability-based operating system.
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// mips/nanonote/threadlist.S: List of initial threads.
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// Copyright 2009 Bas Wijnen <wijnen@debian.org>
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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.globl init_start
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.globl thread_start
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.set noreorder
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.balign 0x1000
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thread0:
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.incbin "fs/bootinit.elf"
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.balign 0x1000
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thread1:
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.incbin "fs/udc.elf"
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.balign 0x1000
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thread2:
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// Everything from here may be freed after kernel initialization.
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init_start:
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thread_start:
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.word thread0
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.word thread1
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.word thread2
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@ -19,6 +19,27 @@
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.globl thread_start
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.set noreorder
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#if defined (UDCBOOT)
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.balign 0x1000
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thread0:
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.incbin "fs/bootinit.elf"
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.balign 0x1000
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thread1:
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.incbin "fs/udc.elf"
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.balign 0x1000
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thread2:
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// Everything from here may be freed after kernel initialization.
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init_start:
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thread_start:
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.word thread0
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.word thread1
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.word thread2
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#elif defined (SDBOOT)
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.balign 0x1000
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thread0:
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.incbin "fs/bootinit.elf"
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@ -46,4 +67,31 @@ thread_start:
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.word thread1
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.word thread2
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.word thread3
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.word thread4
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#elif defined (UNBRICK)
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.balign 0x1000
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thread0:
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.incbin "fs/bootinit.elf"
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.balign 0x1000
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thread1:
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.incbin "fs/nand.elf"
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.balign 0x1000
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thread2:
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.incbin "fs/usb-mass-storage.elf"
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.balign 0x1000
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thread3:
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// Everything from here may be freed after kernel initialization.
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init_start:
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thread_start:
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.word thread0
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.word thread1
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.word thread2
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.word thread3
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#else
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#error "boot method not defined"
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#endif
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135
mips/nanonote/unbrick.ccp
Normal file
135
mips/nanonote/unbrick.ccp
Normal file
@ -0,0 +1,135 @@
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#pypp 0
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// Iris: micro-kernel for a capability-based operating system.
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// mips/nanonote/unbrick.ccp: Host-side helper for USB boot.
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// Copyright 2009-2010 Bas Wijnen <wijnen@debian.org>
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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#include <unistd.h>
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#include <usb.h>
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#include <fstream>
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#include <sstream>
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#include <iostream>
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#include <iomanip>
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#include <cstring>
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#include <shevek/args.hh>
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#include <shevek/error.hh>
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#define STAGE1_FILE "stage1.raw"
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static usb_dev_handle *handle
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static int const boot_vendor = 0x601a
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static int const boot_product = 0x4740
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static int const run_vendor = 0xfffe
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static int const run_product = 0x0002
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static unsigned const timeout = 10000
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void boot (std::string const &filename, unsigned load, unsigned entry)
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static unsigned const STAGE1_LOAD = 0x80002000
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static unsigned const STAGE1_ENTRY = STAGE1_LOAD
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enum requests:
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VR_GET_CPU_INFO = 0
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VR_SET_DATA_ADDRESS = 1
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VR_SET_DATA_LENGTH = 2
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VR_FLUSH_CACHES = 3
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VR_PROGRAM_START1 = 4
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VR_PROGRAM_START2 = 5
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void request (requests num, unsigned data = 0)
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void get_device (unsigned vendor, unsigned product, unsigned tries)
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void request (requests r, unsigned data):
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if usb_control_msg (handle, USB_ENDPOINT_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, r, (data >> 16) & 0xffff, data & 0xffff, NULL, 0, timeout) < 0:
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std::cerr << "unable to send control message to NanoNote: " << usb_strerror () << ".\n"
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usb_release_interface (handle, 0)
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usb_close (handle)
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handle = NULL
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void send_file (unsigned address, int size, char const *data):
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request (VR_SET_DATA_ADDRESS, address)
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char const *ptr = data
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while ptr - data < size:
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int ret = usb_bulk_write (handle, 1, ptr, size - (ptr - data), timeout)
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if ret <= 0:
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std::cerr << "failed to write to NanoNote.\n"
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usb_release_interface (handle, 0)
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usb_close (handle)
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handle = NULL
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return
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ptr += ret
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void get_device (unsigned vendor, unsigned product, unsigned tries):
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for unsigned i = 0; i < tries; ++i:
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usb_find_busses ()
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usb_find_devices ()
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for struct usb_bus *bus = usb_busses; bus; bus = bus->next:
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for struct usb_device *dev = bus->devices; dev; dev = dev->next:
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if dev->descriptor.idProduct != product || dev->descriptor.idVendor != vendor:
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//std::cerr << shevek::ostring ("Not using %04x:%04x when looking for %04x:%04x\n", dev->descriptor.idVendor, dev->descriptor.idProduct, vendor, product)
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continue
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handle = usb_open (dev)
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if usb_claim_interface (handle, 0) < 0:
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std::cerr << "unable to claim interface: " << usb_strerror () << "\n"
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usb_close (handle)
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handle = NULL
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continue
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return
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if i + 1 < tries:
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//std::cerr << "failed to find device, still trying...\n"
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sleep (1)
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std::cerr << shevek::ostring ("giving up finding device %04x:%04x\n", vendor, product)
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void boot (std::string const &filename, unsigned load, unsigned entry):
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std::cerr << "booting " << shevek::ostring ("%s from %x@%x", Glib::ustring (filename), load, entry) << "\n"
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get_device (boot_vendor, boot_product, 1)
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if !handle:
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std::cerr << "unable to find device\n"
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return
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std::cerr << "sending stage 1\n"
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std::ifstream file (STAGE1_FILE)
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std::ostringstream stage1
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stage1 << file.rdbuf ()
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send_file (STAGE1_LOAD, stage1.str ().size (), stage1.str ().data ())
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std::cerr << "running stage 1\n"
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request (VR_PROGRAM_START1, STAGE1_ENTRY)
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usleep (100)
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std::ostringstream stage2
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usb_release_interface (handle, 0)
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file.close ()
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file.open (filename.c_str ())
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stage2 << file.rdbuf ()
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std::cerr << shevek::ostring ("sending Iris (size 0x%x)\n", stage2.str ().size ())
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send_file (load, stage2.str ().size (), stage2.str ().data ())
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std::cerr << "flushing caches\n"
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request (VR_FLUSH_CACHES)
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std::cerr << "running Iris\n"
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request (VR_PROGRAM_START2, entry)
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usb_release_interface (handle, 0)
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usb_close (handle)
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handle = NULL
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std::cerr << "done\n"
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int main (int argc, char **argv):
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std::string filename ("iris.raw")
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unsigned load (0x80000000), entry (0)
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handle = NULL
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usb_init ()
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shevek::args::option opts[] = {
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shevek::args::option ('f', "file", "image file", true, filename),
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shevek::args::option ('l', "load", "load address", true, load),
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shevek::args::option ('e', "entry", "entry point address", false, entry)
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}
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shevek::args args (argc, argv, opts, 0, 0, "unbrick program for NanoNote", "2009-2010")
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if !entry:
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shevek_error ("You must specify the entry point")
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boot (filename, load, entry)
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return 0
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@ -30,7 +30,7 @@ static bool dirty
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static unsigned current_block
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static void sync ():
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Iris::debug ("erasing %x\n", current_block << block_bits)
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//Iris::debug ("erasing %x\n", current_block << block_bits)
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erase (current_block << block_bits)
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for unsigned p = 0; p < 1 << (block_bits - page_bits); ++p:
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write ((current_block << block_bits) + (p << page_bits), (char *)&cache[p << (page_bits - 2)])
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@ -28,20 +28,15 @@ IDLE: after reset or csw.
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IN interrupt: csw received, do nothing.
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OUT interrupt: cbw; handle
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-> IDLE (no data; csw sent)
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-> CSW (data sent in one packet)
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-> TX (more than one packet to send)
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-> TX (send)
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-> RX (receive packets)
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TX: transmitting data.
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IN interrupt: host received data; send more.
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-> TX (more to send)
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-> CSW (last data has now been sent)
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RX: receiving data.
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OUT interrupt: host sent data; handle.
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-> RX (more to receive)
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-> IDLE (done receiving; send csw)
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CSW: waiting to transmit csw.
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IN interrupt: TX is done; send csw
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-> IDLE
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#endif
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extern "C":
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@ -218,17 +213,27 @@ class Udc:
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char configuration
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unsigned get_descriptor (unsigned type, unsigned idx, unsigned len)
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unsigned handle_setup (Setup *s)
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void irq_usb ()
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void reset ()
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void irq_in0 ()
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void irq_out ()
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void handle_rx ()
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void handle_tx ()
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void handle_cbw ()
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void send_csw ()
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unsigned big_endian (unsigned src)
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bool handle_interrupt (bool usb, bool in)
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void stall (unsigned error)
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bool stalling[3]
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bool stalling
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enum State:
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IDLE
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TX
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RX
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SENT_CSW
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STALL
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State state
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unsigned residue
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unsigned status
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unsigned tag
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unsigned data_done, lba, blocks
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unsigned block_bits
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Iris::WBlock block
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Iris::Page buffer_page
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@ -248,6 +253,35 @@ Udc::String <6> Udc::s_manufacturer
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Udc::String <16> Udc::s_product
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Udc::String <12> Udc::s_serial
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void Udc::reset ():
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// Reset.
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UDC_TESTMODE = 0
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configuration = 0
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state = IDLE
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status = 0
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residue = 0
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// enable interrupt on bus reset.
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UDC_INTRUSBE = UDC_INTR_RESET
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// enable interrupts on endpoint 0 and in endpoint 2
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UDC_INTRINE = 1 << 0 | 1 << 2
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// and on out endpoint 1.
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UDC_INTROUTE = 1 << 1
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// exit suspend mode by reading the interrupt register.
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unsigned i = UDC_INTRUSB
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// reset all pending endpoint interrupts.
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i = UDC_INTRIN
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i = UDC_INTROUT
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UDC_INDEX = 1
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UDC_OUTMAXP = max_packet_size_bulk
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// Do this twice to flush a double-buffered fifo completely.
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||||
UDC_OUTCSR |= UDC_OUTCSR_CDT | UDC_OUTCSR_FF
|
||||
UDC_OUTCSR |= UDC_OUTCSR_CDT | UDC_OUTCSR_FF
|
||||
UDC_INDEX = 2
|
||||
UDC_INMAXP = max_packet_size_bulk
|
||||
UDC_INCSR = (UDC_INCSRH_MODE << 8) | UDC_INCSR_CDT | UDC_INCSR_FF
|
||||
UDC_INCSR = (UDC_INCSRH_MODE << 8) | UDC_INCSR_CDT | UDC_INCSR_FF
|
||||
//Iris::debug ("usb reset\n")
|
||||
|
||||
void Udc::init (Iris::WBlock b):
|
||||
block = b
|
||||
block_bits = block.get_align_bits ()
|
||||
@ -272,37 +306,12 @@ void Udc::init (Iris::WBlock b):
|
||||
cpm_start_udc ()
|
||||
// Disconnect from the bus and don't try to get high-speed.
|
||||
UDC_POWER = 0
|
||||
UDC_TESTMODE = 0
|
||||
configuration = 0
|
||||
// Set max packet sizes.
|
||||
UDC_INDEX = 1
|
||||
UDC_OUTMAXP = max_packet_size_bulk
|
||||
UDC_OUTCSR = UDC_OUTCSR_CDT | UDC_OUTCSR_FF
|
||||
UDC_OUTCSR = UDC_OUTCSR_CDT | UDC_OUTCSR_FF
|
||||
UDC_INDEX = 2
|
||||
UDC_INMAXP = max_packet_size_bulk
|
||||
UDC_INCSR = (UDC_INCSRH_MODE << 8) | UDC_INCSR_CDT | UDC_INCSR_FF
|
||||
UDC_INCSR = (UDC_INCSRH_MODE << 8) | UDC_INCSR_CDT | UDC_INCSR_FF
|
||||
// exit suspend mode by reading the interrupt register.
|
||||
unsigned i = UDC_INTRUSB
|
||||
// reset all pending endpoint interrupts.
|
||||
i = UDC_INTRIN
|
||||
i = UDC_INTROUT
|
||||
// enable interrupt on bus reset.
|
||||
UDC_INTRUSBE = UDC_INTR_RESET
|
||||
// enable interrupts on endpoint 0 and in endpoint 2
|
||||
UDC_INTRINE = 1 << 0 | 1 << 2
|
||||
// and on out endpoint 1.
|
||||
UDC_INTROUTE = 1 << 1
|
||||
reset ()
|
||||
// Wait a while.
|
||||
Iris::sleep (HZ / 10)
|
||||
// Connect to the host.
|
||||
UDC_POWER = UDC_POWER_SOFTCONN
|
||||
|
||||
// Initialize cbw state
|
||||
status = 0
|
||||
residue = 0
|
||||
|
||||
void Udc::send (unsigned ep, char const *data, unsigned length, unsigned maxlength):
|
||||
if maxlength < length:
|
||||
length = maxlength
|
||||
@ -318,8 +327,6 @@ void Udc::send (unsigned ep, char const *data, unsigned length, unsigned maxleng
|
||||
|
||||
void Udc::send_padded (char const *data, unsigned length, unsigned maxlength):
|
||||
UDC_INDEX = 2
|
||||
if UDC_INCSR & UDC_INCSR_INPKTRDY:
|
||||
Iris::panic (0, "sending padded not possible because a packet is already waiting.\n")
|
||||
unsigned len = length < maxlength ? length : maxlength
|
||||
residue = maxlength - len
|
||||
len = (len + 3) & ~3
|
||||
@ -328,48 +335,14 @@ void Udc::send_padded (char const *data, unsigned length, unsigned maxlength):
|
||||
while len + 3 < maxlength:
|
||||
UDC_FIFO (2) = 0
|
||||
len += 4
|
||||
if len % max_packet_size_bulk == 0:
|
||||
// This doesn't ever happen, because the largest packet we send is smaller than max_packet_size_bulk.
|
||||
Iris::debug ("sending at len %x\n", len)
|
||||
UDC_INCSR |= UDC_INCSR_INPKTRDY
|
||||
while true:
|
||||
Iris::register_interrupt (IRQ_UDC)
|
||||
Iris::wait_for_interrupt (IRQ_UDC)
|
||||
kdebug ("interrupt pad0\n")
|
||||
unsigned usb = UDC_INTRUSB
|
||||
unsigned in = UDC_INTRIN
|
||||
if usb & 4 || in & 1:
|
||||
//kdebug ("general interrupt pad0\t")
|
||||
if !handle_interrupt (usb & 4, in & 1):
|
||||
return
|
||||
unsigned out = UDC_INTROUT
|
||||
if out & 2:
|
||||
Iris::panic (0, "out interrupt while waiting for in")
|
||||
if in & 4:
|
||||
break
|
||||
//kdebug_char ('-')
|
||||
if len % max_packet_size_bulk != 0 || len < maxlength:
|
||||
while len < maxlength:
|
||||
UDC_FIFO8 (2) = 0
|
||||
++len
|
||||
//kdebug_char ('.')
|
||||
UDC_INCSR |= UDC_INCSR_INPKTRDY
|
||||
while true:
|
||||
Iris::register_interrupt (IRQ_UDC)
|
||||
Iris::wait_for_interrupt (IRQ_UDC)
|
||||
kdebug ("interrupt pad\t")
|
||||
unsigned usb = UDC_INTRUSB
|
||||
unsigned in = UDC_INTRIN
|
||||
if usb & 4 || in & 1:
|
||||
//kdebug ("general interrupt pad\t")
|
||||
if !handle_interrupt (usb & 4, in & 1):
|
||||
return
|
||||
unsigned out = UDC_INTROUT
|
||||
if out & 2:
|
||||
Iris::panic (0, "out interrupt while waiting for in")
|
||||
if in & 4:
|
||||
break
|
||||
//kdebug ("done interrupt pad\n")
|
||||
while len < maxlength:
|
||||
UDC_FIFO8 (2) = 0
|
||||
++len
|
||||
//kdebug_char ('.')
|
||||
UDC_INCSR |= UDC_INCSR_INPKTRDY
|
||||
blocks = 0
|
||||
state = TX
|
||||
|
||||
unsigned Udc::get_descriptor (unsigned type, unsigned idx, unsigned len):
|
||||
switch type:
|
||||
@ -424,18 +397,18 @@ unsigned Udc::handle_setup (Setup *s):
|
||||
switch s->request:
|
||||
case SET_ADDRESS:
|
||||
UDC_FADDR = s->value
|
||||
//Iris::debug ("set address %x\n", s->value)
|
||||
Iris::debug ("set address %x\n", s->value)
|
||||
return 0
|
||||
case SET_CONFIGURATION:
|
||||
if s->value >= 2:
|
||||
return ~0
|
||||
configuration = s->value
|
||||
//Iris::debug ("set configuration %x\n", s->value)
|
||||
Iris::debug ("set configuration %x\n", s->value)
|
||||
return 0
|
||||
case SET_INTERFACE:
|
||||
if s->value != 0:
|
||||
return ~0
|
||||
//Iris::debug ("set interface %x\n", s->value)
|
||||
Iris::debug ("set interface %x\n", s->value)
|
||||
return 0
|
||||
default:
|
||||
return ~0
|
||||
@ -444,17 +417,17 @@ unsigned Udc::handle_setup (Setup *s):
|
||||
UDC_CSR0 = UDC_CSR0_DATAEND | UDC_CSR0_SVDOUTPKTRDY
|
||||
switch s->request:
|
||||
case GET_STATUS:
|
||||
//Iris::debug ("get status\t")
|
||||
Iris::debug ("get status\t")
|
||||
send (0, "\0\0", 2, s->length)
|
||||
return UDC_CSR0_INPKTRDY | UDC_CSR0_DATAEND
|
||||
case GET_DESCRIPTOR:
|
||||
return get_descriptor ((s->value >> 8) & 0xff, s->value & 0xff, s->length)
|
||||
case GET_CONFIGURATION:
|
||||
//Iris::debug ("get configuration\t")
|
||||
Iris::debug ("get configuration\t")
|
||||
send (0, &configuration, 1, s->length)
|
||||
return UDC_CSR0_INPKTRDY | UDC_CSR0_DATAEND
|
||||
case GET_INTERFACE:
|
||||
//Iris::debug ("get interface\t")
|
||||
Iris::debug ("get interface\t")
|
||||
send (0, "\0", 1, s->length)
|
||||
return UDC_CSR0_INPKTRDY | UDC_CSR0_DATAEND
|
||||
default:
|
||||
@ -466,16 +439,16 @@ unsigned Udc::handle_setup (Setup *s):
|
||||
case ENDPOINT_HALT:
|
||||
switch s->index:
|
||||
case 0x82:
|
||||
Iris::debug ("in ep halt reset\n")
|
||||
//Iris::debug ("in ep halt reset\n")
|
||||
UDC_INDEX = 2
|
||||
UDC_INCSR &= ~UDC_INCSR_SENDSTALL
|
||||
stalling[2] = false
|
||||
UDC_INCSR = (UDC_INCSR & ~UDC_INCSR_SENDSTALL) | UDC_INCSR_CDT
|
||||
stalling = false
|
||||
send_csw ()
|
||||
break
|
||||
case 1:
|
||||
Iris::debug ("out ep halt reset\n")
|
||||
//Iris::panic (0, "halt reset on out endpoint")
|
||||
UDC_INDEX = 1
|
||||
UDC_OUTCSR &= ~UDC_OUTCSR_SENDSTALL
|
||||
stalling[1] = false
|
||||
UDC_OUTCSR |= UDC_OUTCSR_CDT
|
||||
break
|
||||
default:
|
||||
return ~0
|
||||
@ -499,7 +472,8 @@ unsigned Udc::handle_setup (Setup *s):
|
||||
UDC_CSR0 = UDC_CSR0_DATAEND | UDC_CSR0_SVDOUTPKTRDY
|
||||
switch s->request:
|
||||
case BULK_ONLY_RESET:
|
||||
//Iris::debug ("bulk reset\n")
|
||||
Iris::debug ("bulk reset\n")
|
||||
state = IDLE
|
||||
return 0
|
||||
default:
|
||||
return ~0
|
||||
@ -507,52 +481,32 @@ unsigned Udc::handle_setup (Setup *s):
|
||||
Iris::debug ("request: %x %x %x %x %x\n", s->request_type, s->request, s->index, s->length, s->value)
|
||||
return ~0
|
||||
|
||||
void Udc::irq_usb ():
|
||||
// Reset.
|
||||
// enable interrupts on endpoint 0 and in endpoint 2
|
||||
UDC_INTRINE = 1 << 0 | 1 << 2
|
||||
// and on out endpoint 1.
|
||||
UDC_INTROUTE = 1 << 1
|
||||
UDC_INDEX = 1
|
||||
// Do this twice to flush a double-buffered fifo completely.
|
||||
UDC_OUTMAXP = max_packet_size_bulk
|
||||
UDC_OUTCSR |= UDC_OUTCSR_CDT | UDC_OUTCSR_FF
|
||||
UDC_OUTCSR |= UDC_OUTCSR_CDT | UDC_OUTCSR_FF
|
||||
UDC_INDEX = 2
|
||||
UDC_INMAXP = max_packet_size_bulk
|
||||
UDC_INCSR |= UDC_INCSR_CDT
|
||||
//Iris::debug ("usb reset\n")
|
||||
|
||||
void Udc::irq_in0 ():
|
||||
// Interrupt on endpoint 0.
|
||||
UDC_INDEX = 0
|
||||
unsigned csr = UDC_CSR0
|
||||
if csr & UDC_CSR0_SENTSTALL:
|
||||
UDC_CSR0 = 0
|
||||
//Iris::debug ("stall done\t")
|
||||
//Iris::debug ("stall 0 done\t")
|
||||
if csr & UDC_CSR0_SETUPEND:
|
||||
UDC_CSR0 = UDC_CSR0_SVDSETUPEND
|
||||
//Iris::debug ("setup aborted\t")
|
||||
Iris::debug ("setup aborted\t")
|
||||
if !(csr & UDC_CSR0_OUTPKTRDY):
|
||||
//Iris::debug ("no packet 0: %x\n", csr)
|
||||
return
|
||||
UDC_INDEX = 1
|
||||
UDC_OUTCSR |= UDC_OUTCSR_CDT
|
||||
UDC_INDEX = 2
|
||||
UDC_INCSR |= UDC_INCSR_CDT
|
||||
UDC_INDEX = 0
|
||||
union { unsigned d[2]; Setup s; } packet
|
||||
packet.d[0] = UDC_FIFO (0)
|
||||
packet.d[1] = UDC_FIFO (0)
|
||||
if !(packet.s.request_type & 0x80) && packet.s.length > 0:
|
||||
// More data will follow; unsupported.
|
||||
//Iris::debug ("packet on ep0 too long\n")
|
||||
Iris::debug ("packet on ep0 too long\n")
|
||||
UDC_CSR0 = UDC_CSR0_SENDSTALL
|
||||
return
|
||||
unsigned ret = handle_setup (&packet.s)
|
||||
UDC_INDEX = 0
|
||||
if ret == ~0:
|
||||
Iris::debug ("failed setup: %x %x %x %x %x\n", packet.s.request_type, packet.s.request, packet.s.index, packet.s.length, packet.s.value)
|
||||
//Iris::debug ("failed setup: %x %x %x %x %x\n", packet.s.request_type, packet.s.request, packet.s.index, packet.s.length, packet.s.value)
|
||||
UDC_CSR0 = UDC_CSR0_SENDSTALL
|
||||
return
|
||||
if ret:
|
||||
@ -566,79 +520,73 @@ void Udc::send_csw ():
|
||||
UDC_FIFO (2) = residue
|
||||
UDC_FIFO8 (2) = status
|
||||
UDC_INCSR |= UDC_INCSR_INPKTRDY
|
||||
state = SENT_CSW
|
||||
status = 0
|
||||
residue = 0
|
||||
while true:
|
||||
Iris::register_interrupt (IRQ_UDC)
|
||||
Iris::wait_for_interrupt (IRQ_UDC)
|
||||
kdebug ("interrupt csw\n")
|
||||
unsigned usb = UDC_INTRUSB
|
||||
unsigned in = UDC_INTRIN
|
||||
if usb & 4 || in & 1:
|
||||
if !handle_interrupt (usb & 4, in & 1):
|
||||
return
|
||||
if in & 4:
|
||||
break
|
||||
unsigned out = UDC_INTROUT
|
||||
if out & 2:
|
||||
Iris::panic (0, "out interrupt while waiting for in after csw")
|
||||
kdebug ("sent csw\n")
|
||||
//kdebug ("sent csw\n")
|
||||
|
||||
void Udc::stall (unsigned error):
|
||||
unsigned index = UDC_INDEX
|
||||
if stalling[index]:
|
||||
if stalling:
|
||||
Iris::debug ("already stalling!\n")
|
||||
if index == 1:
|
||||
UDC_OUTCSR |= UDC_OUTCSR_SENDSTALL
|
||||
else:
|
||||
UDC_INCSR |= UDC_INCSR_SENDSTALL
|
||||
stalling[index] = true
|
||||
while stalling[index]:
|
||||
//Iris::debug ("stalling %d\n", index)
|
||||
Iris::register_interrupt (IRQ_UDC)
|
||||
Iris::wait_for_interrupt (IRQ_UDC)
|
||||
kdebug ("stalling interrupt\n")
|
||||
unsigned usb = UDC_INTRUSB
|
||||
unsigned in = UDC_INTRIN
|
||||
if in & 4:
|
||||
if index != 2:
|
||||
Iris::panic (0, "stalling on out, but in responds")
|
||||
kdebug ("stall has been sent to in endpoint\n")
|
||||
UDC_INDEX = 2
|
||||
UDC_INCSR &= ~UDC_INCSR_SENTSTALL
|
||||
//Iris::debug ("csr: %x\n", UDC_INCSR)
|
||||
if usb & 4 || in & 1:
|
||||
//kdebug ("stuff\n")
|
||||
if !handle_interrupt (usb & 4, in & 1):
|
||||
return
|
||||
unsigned out = UDC_INTROUT
|
||||
if out & 2:
|
||||
if index != 1:
|
||||
Iris::panic (0, "stalling on in, but out responds")
|
||||
kdebug ("stall has been sent to out endpoint\n")
|
||||
UDC_INDEX = 1
|
||||
UDC_OUTCSR &= ~UDC_OUTCSR_SENTSTALL
|
||||
//kdebug ("done stalling\n")
|
||||
if index == 2:
|
||||
status = error
|
||||
send_csw ()
|
||||
UDC_INCSR |= UDC_INCSR_SENDSTALL
|
||||
stalling = true
|
||||
state = STALL
|
||||
|
||||
unsigned Udc::big_endian (unsigned src):
|
||||
return src >> 24 | src >> 8 & 0xff00 | src << 8 & 0xff0000 | src << 24
|
||||
|
||||
void Udc::irq_out ():
|
||||
void Udc::handle_rx ():
|
||||
buffer_page.set_flags (Iris::Page::FRAME)
|
||||
UDC_INDEX = 1
|
||||
if !(UDC_OUTCSR & UDC_OUTCSR_OUTPKTRDY):
|
||||
Iris::panic (0, "no packet ready after out interrupt during rx")
|
||||
if UDC_OUTCOUNT != max_packet_size_bulk:
|
||||
Iris::panic (UDC_OUTCOUNT, "invalid packet size during rx")
|
||||
for unsigned t = 0; t < max_packet_size_bulk; t += 4:
|
||||
((unsigned *)buffer)[(t + data_done) >> 2] = UDC_FIFO (1)
|
||||
UDC_OUTCSR &= ~UDC_OUTCSR_OUTPKTRDY
|
||||
data_done += max_packet_size_bulk
|
||||
if data_done == 1 << block_bits:
|
||||
//Iris::debug ("writing block %x\n", lba)
|
||||
block.set_block (lba << block_bits, buffer_page, 1 << block_bits)
|
||||
data_done = 0
|
||||
--blocks
|
||||
++lba
|
||||
if blocks == 0:
|
||||
send_csw ()
|
||||
return
|
||||
|
||||
void Udc::handle_tx ():
|
||||
if blocks == 0:
|
||||
send_csw ()
|
||||
return
|
||||
if data_done == 0:
|
||||
// read block lba.
|
||||
buffer_page.set_flags (Iris::Page::FRAME)
|
||||
block.get_block (lba << block_bits, 1 << block_bits, 0, buffer_page)
|
||||
UDC_INDEX = 2
|
||||
for unsigned t = 0; t < max_packet_size_bulk; t += 4:
|
||||
UDC_FIFO (2) = ((unsigned *)buffer)[(data_done + t) >> 2]
|
||||
data_done += max_packet_size_bulk
|
||||
if data_done == 1 << block_bits:
|
||||
data_done = 0
|
||||
++lba
|
||||
--blocks
|
||||
UDC_INCSR |= UDC_INCSR_INPKTRDY
|
||||
|
||||
void Udc::handle_cbw ():
|
||||
UDC_INDEX = 1
|
||||
unsigned csr = UDC_OUTCSR
|
||||
unsigned size = UDC_OUTCOUNT
|
||||
if !(csr & UDC_OUTCSR_OUTPKTRDY):
|
||||
// No packet, just a notification.
|
||||
kdebug ("no packet\n")
|
||||
return
|
||||
if csr & UDC_OUTCSR_SENDSTALL:
|
||||
// When stalling, do nothing else.
|
||||
//kdebug ("not responding to out during stall\n")
|
||||
UDC_OUTCSR = csr & ~UDC_OUTCSR_SENTSTALL
|
||||
return
|
||||
if !(csr & UDC_OUTCSR_OUTPKTRDY):
|
||||
// No packet; this shouldn't happen.
|
||||
Iris::panic (0, "no packet")
|
||||
return
|
||||
// expect a new cbw.
|
||||
if size != 31:
|
||||
Iris::debug ("count %d != 31\n", size)
|
||||
@ -656,10 +604,17 @@ void Udc::irq_out ():
|
||||
UDC_OUTCSR = csr & ~UDC_OUTCSR_OUTPKTRDY
|
||||
tag = cbw.cbw.tag
|
||||
if cbw.cbw.sig != 0x43425355 || cbw.cbw.lun != 0 || cbw.cbw.size == 0 || cbw.cbw.size > 16:
|
||||
Iris::debug ("sig %x lun %d size %d\n", cbw.cbw.sig, cbw.cbw.lun, cbw.cbw.size)
|
||||
Iris::debug ("wrong cbw: sig %x lun %d size %d\n", cbw.cbw.sig, cbw.cbw.lun, cbw.cbw.size)
|
||||
stall (2)
|
||||
return
|
||||
//kdebug ("bulk cbw\t")
|
||||
#if 0
|
||||
Iris::debug ("cbw:")
|
||||
for unsigned i = 0; i < cbw.cbw.size; ++i:
|
||||
kdebug_char (' ')
|
||||
kdebug_num (cbw.cbw.data[i], 2)
|
||||
Iris::debug ("\n")
|
||||
#endif
|
||||
UDC_INDEX = 2
|
||||
bool to_host = cbw.cbw.flags & 0x80
|
||||
switch cbw.cbw.data[0]:
|
||||
@ -673,7 +628,6 @@ void Udc::irq_out ():
|
||||
case CBW::REQUEST_SENSE:
|
||||
//Iris::debug ("sense requested\n")
|
||||
send_padded ("\xf0\x00\x05\x00\x00\x00\x00\x00", 8, cbw.cbw.length)
|
||||
send_csw ()
|
||||
break
|
||||
case CBW::FORMAT_UNIT:
|
||||
Iris::panic (0, "FORMAT_UNIT isn't implemented")
|
||||
@ -682,8 +636,8 @@ void Udc::irq_out ():
|
||||
stall (2)
|
||||
return
|
||||
//Iris::debug ("sending inquiry response\t")
|
||||
// TODO: find out why these bytes are messed up.
|
||||
send_padded ("\x00\x00\x04\x02\x1f\x00\x00\x00shevek iris usb stick \x00\x00\x04\x02", 36, cbw.cbw.length)
|
||||
send_csw ()
|
||||
break
|
||||
case CBW::RESERVE6:
|
||||
Iris::panic (0, "RESERVE6 isn't implemented")
|
||||
@ -700,118 +654,94 @@ void Udc::irq_out ():
|
||||
capacity[1] = big_endian (1 << block_bits)
|
||||
//Iris::debug ("sending capacity: %x * %x\t", capacity[0], capacity[1])
|
||||
send_padded ((char *)capacity, 8, cbw.cbw.length)
|
||||
send_csw ()
|
||||
break
|
||||
case CBW::READ10:
|
||||
unsigned lba = cbw.cbw.data[2] << 24 | cbw.cbw.data[3] << 16 | cbw.cbw.data[4] << 8 | cbw.cbw.data[5]
|
||||
unsigned blocks = cbw.cbw.data[7] << 8 | cbw.cbw.data[8]
|
||||
for unsigned i = 0; i < blocks; ++i:
|
||||
//Iris::debug ("reading block %d\n", lba + i)
|
||||
// read block lba + i.
|
||||
buffer_page.set_flags (Iris::Page::FRAME)
|
||||
block.get_block ((lba + i) << block_bits, 1 << block_bits, 0, buffer_page)
|
||||
for unsigned p = 0; p < 1 << block_bits; p += max_packet_size_bulk:
|
||||
//Iris::debug (" %d", p)
|
||||
UDC_INDEX = 2
|
||||
for unsigned t = 0; t < max_packet_size_bulk; t += 4:
|
||||
UDC_FIFO (2) = ((unsigned *)buffer)[(p + t) >> 2]
|
||||
UDC_INCSR |= UDC_INCSR_INPKTRDY
|
||||
//Iris::debug ("\n")
|
||||
while true:
|
||||
Iris::register_interrupt (IRQ_UDC)
|
||||
Iris::wait_for_interrupt (IRQ_UDC)
|
||||
kdebug ("interrupt read10\n")
|
||||
unsigned usb = UDC_INTRUSB
|
||||
unsigned in = UDC_INTRIN
|
||||
unsigned out = UDC_INTROUT
|
||||
if usb & 4 || in & 1:
|
||||
//kdebug ("general interrupt read10\t")
|
||||
if !handle_interrupt (usb & 4, in & 1):
|
||||
return
|
||||
if out & 2:
|
||||
Iris::panic (0, "out interrupt while waiting for in")
|
||||
if in & 4:
|
||||
break
|
||||
send_csw ()
|
||||
if !to_host:
|
||||
stall (2)
|
||||
return
|
||||
lba = cbw.cbw.data[2] << 24 | cbw.cbw.data[3] << 16 | cbw.cbw.data[4] << 8 | cbw.cbw.data[5]
|
||||
blocks = cbw.cbw.data[7] << 8 | cbw.cbw.data[8]
|
||||
data_done = 0
|
||||
state = TX
|
||||
handle_tx ()
|
||||
break
|
||||
case CBW::WRITE10:
|
||||
unsigned lba = cbw.cbw.data[2] << 24 | cbw.cbw.data[3] << 16 | cbw.cbw.data[4] << 8 | cbw.cbw.data[5]
|
||||
unsigned blocks = cbw.cbw.data[7] << 8 | cbw.cbw.data[8]
|
||||
for unsigned i = 0; i < blocks; ++i:
|
||||
//Iris::debug ("writing block %d\n", lba + i)
|
||||
// write block lba + i.
|
||||
buffer_page.set_flags (Iris::Page::FRAME)
|
||||
//Iris::debug ("@%x:", (lba + i) << block_bits)
|
||||
for unsigned p = 0; p < 1 << block_bits; p += max_packet_size_bulk:
|
||||
while true:
|
||||
Iris::register_interrupt (IRQ_UDC)
|
||||
Iris::wait_for_interrupt (IRQ_UDC)
|
||||
Iris::debug (".")
|
||||
unsigned usb = UDC_INTRUSB
|
||||
unsigned in = UDC_INTRIN
|
||||
unsigned out = UDC_INTROUT
|
||||
if usb & 4 || in & 1:
|
||||
if !handle_interrupt (usb & 4, in & 1):
|
||||
return
|
||||
if out & 2:
|
||||
break
|
||||
if in & 4:
|
||||
Iris::panic (0, "in interrupt while waiting for out")
|
||||
UDC_INDEX = 1
|
||||
if !(UDC_OUTCSR & UDC_OUTCSR_OUTPKTRDY):
|
||||
Iris::panic (0, "no packet ready after out interrupt in write10")
|
||||
if UDC_OUTCOUNT != max_packet_size_bulk:
|
||||
Iris::panic (UDC_OUTCOUNT, "invalid packet size in write10")
|
||||
for unsigned t = 0; t < max_packet_size_bulk; t += 4:
|
||||
((unsigned *)buffer)[(p + t) >> 2] = UDC_FIFO (1)
|
||||
//kdebug (" ")
|
||||
//kdebug_num (((unsigned *)buffer)[(p + t) >> 2], 8)
|
||||
UDC_OUTCSR &= ~UDC_OUTCSR_OUTPKTRDY
|
||||
//kdebug ("\n")
|
||||
//Iris::debug ("setting block %x@%x+%x\n", lba + i << block_bits, 0, 1 << block_bits)
|
||||
block.set_block ((lba + i) << block_bits, buffer_page, 1 << block_bits)
|
||||
send_csw ()
|
||||
if to_host:
|
||||
stall (2)
|
||||
return
|
||||
lba = cbw.cbw.data[2] << 24 | cbw.cbw.data[3] << 16 | cbw.cbw.data[4] << 8 | cbw.cbw.data[5]
|
||||
blocks = cbw.cbw.data[7] << 8 | cbw.cbw.data[8]
|
||||
if blocks == 0:
|
||||
send_csw ()
|
||||
break
|
||||
state = RX
|
||||
data_done = 0
|
||||
buffer_page.set_flags (Iris::Page::FRAME)
|
||||
break
|
||||
case CBW::RESERVE10:
|
||||
Iris::panic (0, "RESERVE10 isn't implemented")
|
||||
case CBW::RELEASE10:
|
||||
Iris::panic (0, "RELEASE10 isn't implemented")
|
||||
default:
|
||||
Iris::debug ("cbw:")
|
||||
#if 0
|
||||
Iris::debug ("unknown cbw:")
|
||||
for unsigned i = 0; i < cbw.cbw.size; ++i:
|
||||
kdebug_char (' ')
|
||||
kdebug_num (cbw.cbw.data[i], 2)
|
||||
Iris::debug ("\n")
|
||||
#endif
|
||||
residue = cbw.cbw.length
|
||||
stall (1)
|
||||
return
|
||||
|
||||
bool Udc::handle_interrupt (bool usb, bool in):
|
||||
if usb:
|
||||
//Iris::debug ("usb\t")
|
||||
// reset.
|
||||
irq_usb ()
|
||||
return false
|
||||
if in:
|
||||
//Iris::debug ("control\t")
|
||||
// control request
|
||||
irq_in0 ()
|
||||
return true
|
||||
|
||||
void Udc::interrupt ():
|
||||
Iris::debug ("interrupt\n")
|
||||
//Iris::debug ("interrupt, state = %d\n", state)
|
||||
while true:
|
||||
bool action = false
|
||||
unsigned usb = UDC_INTRUSB
|
||||
unsigned in = UDC_INTRIN
|
||||
bool action = false
|
||||
if in & 4:
|
||||
Iris::panic (0, "data request during idle\n")
|
||||
if usb & 4 || in & 1:
|
||||
handle_interrupt (usb & 4, in & 1)
|
||||
action = true
|
||||
unsigned out = UDC_INTROUT
|
||||
if usb & 4:
|
||||
//Iris::debug ("reset\n")
|
||||
reset ()
|
||||
action = true
|
||||
if state == STALL && in & 4:
|
||||
// This must be handled here, because the state can be changed by the control request.
|
||||
//Iris::debug ("stalling\n")
|
||||
in &= ~4
|
||||
if in & 1:
|
||||
//Iris::debug ("control request\n")
|
||||
irq_in0 ()
|
||||
action = true
|
||||
if in & 4:
|
||||
//Iris::debug ("in request\n")
|
||||
// Notification of sent packet (or stall, but we don't do that on the in endpoint).
|
||||
switch state:
|
||||
case SENT_CSW:
|
||||
// csw received.
|
||||
state = IDLE
|
||||
break
|
||||
case TX:
|
||||
handle_tx ()
|
||||
break
|
||||
default:
|
||||
Iris::panic (state, "invalid state for data send")
|
||||
stall (2)
|
||||
break
|
||||
action = true
|
||||
if out & 2:
|
||||
irq_out ()
|
||||
//Iris::debug ("out request\n")
|
||||
switch state:
|
||||
case IDLE:
|
||||
handle_cbw ()
|
||||
break
|
||||
case RX:
|
||||
handle_rx ()
|
||||
break
|
||||
default:
|
||||
stall (2)
|
||||
Iris::panic (0, "invalid state for data receive")
|
||||
break
|
||||
action = true
|
||||
if !action:
|
||||
// No more interrupts to handle; this is normal, because we're looping until this happens.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user