Adding iverilog simulation support

Examples/blink/logic/Makefile

@@ -7,9 +7,18 @@ BGFLAGS         = -g TdoPin:PULLNONE -g DonePin:PULLUP \
 SIM_CMD         = vsim 
 SIM_COMP_SCRIPT = simulation/$(DESIGN)_TB.do
 SIMGEN_OPTIONS  = -p $(FPGA_ARCH) -lang $(LANGUAGE)
+IVERILOG        = iverilog
+
 SAKC_IP         = 192.168.254.101
 
 SRC             = $(DESIGN).v 
+
+SIM_SRC = $(DESIGN)_TB.v          \
+	sim/unisims/BUFG.v        \
+	sim/unisims/DCM.v         \
+	sim/unisims/FDDRRSE.v
+
+
  
 all:            bits
 
@@ -20,7 +29,7 @@ clean:
 	rm -f *.bit
 
 cleanall: clean
-	rm -rf build simulation/work simulation/transcript  simulation/vsim.wlf
+	rm -rf build simulation/work simulation/transcript  simulation/vsim.wlf simulation/blink_TB.vvp simulation/blink_TB.vcd
 
 bits:           $(DESIGN).bit
 
@@ -65,13 +74,18 @@ $(DESIGN).bit:  build/project_r.ncd build/project_r.twr
 	@mv -f build/project_r.bit $@
 
 build/project_r.v: build/project_r.ncd
-	cd build &&  netgen -sim -ofmt vhdl project_r.ncd -pcf project.pcf && ngd2ver project.ngd  -w project.v
+	cd build &&  netgen -sim -ofmt vhdl project_r.ncd -pcf project.pcf && ngd2ver projecsimulationt.ngd  -w project.v
 
-sim: 
+modelsim: 
 	cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do
 
 timesim: build/project_r.v
 	cd simulation; $(SIM_CMD) -do $(DESIGN)_TIMING_TB.do
 
+iversim:
+	$(IVERILOG) -o simulation/$(DESIGN)_TB.vvp $(VINCDIR) $(SRC) $(SIM_SRC) -s $(DESIGN)_TB_v
+	vvp simulation/$(DESIGN)_TB.vvp; mv $(DESIGN)_TB.vcd simulation/
+	gtkwave simulation/$(DESIGN)_TB.vcd&
+
 upload: $(DESIGN).bit
 	scp $(DESIGN).bit root@$(SAKC_IP): 

Examples/blink/logic/blink_TB.v

@@ -43,8 +43,12 @@ module blink_TB_v;
    end
 	 
 
-   initial begin: TEST_CASE	
+   initial begin: TEST_CASE
+     $dumpfile("blink_TB.vcd");
+     $dumpvars(-1, uut);
+	
      #10 -> reset_trigger;
+     #((PERIOD*DUTY_CYCLE)*100) $finish;
    end
 
 endmodule