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Adding iverilog simulation support

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This commit is contained in:
Carlos Camargo
2010-05-12 09:36:30 -05:00
parent 23184f39dd
commit 079d8042f6
15 changed files with 72 additions and 30 deletions
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22
Examples/sram/logic/Makefile
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@@ -8,9 +8,21 @@ SIM_CMD = /opt/cad/modeltech/bin/vsim
SIM_COMP_SCRIPT = simulation/$(DESIGN)_TB.do
SIMGEN_OPTIONS = -p $(FPGA_ARCH) -lang $(LANGUAGE)
SAKC_IP = 192.168.254.101
IVERILOG = iverilog
XILINXCADROOT = /opt/cad/Xilinx/verilog/src
#XILINXCADROOT = /opt/cad/modeltech/xilinx/verilog/
SRC = sram_bus.v
SIM_SRC = $(DESIGN)_TB.v \
# sim/unisims/BUFG.v \
# sim/unisims/DCM.v \
# sim/unisims/FDDRRSE.v \
# glbl.v
# sim/unisims/RAMB16_S2_S9.v
all: bits
remake: clean-build all
@@ -70,11 +82,17 @@ $(DESIGN).bit: build/project_r.ncd build/project_r.twr
build/project_r.v: build/project_r.ncd
cd build && netgen -sim -ofmt vhdl project_r.ncd -pcf project.pcf && ngd2ver project.ngd -w project.v
sim:
modelsim:
cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do
timesim: build/project_r.v
cd simulation; $(SIM_CMD) -do $(DESIGN)_TIMING_TB.do
iversim:
$(IVERILOG) -Wall -y $(XILINXCADROOT)/unisims -y $(XILINXCADROOT)/XilinxCoreLib -o simulation/$(DESIGN)_TB.vvp $(VINCDIR) $(SRC) $(SIM_SRC) -s $(DESIGN)_TB
# $(IVERILOG) -Wall -y $(XILINXCADROOT)/unisims -y $(XILINXCADROOT)/XilinxCoreLib -o simulation/$(DESIGN)_TB.vvp $(VINCDIR) build/project.v $(SIM_SRC) -s $(DESIGN)_TB
vvp simulation/$(DESIGN)_TB.vvp; mv $(DESIGN)_TB.vcd simulation/
gtkwave simulation/$(DESIGN)_TB.vcd&
upload: $(DESIGN).bit
scp $(DESIGN).bit root@$(SAKC_IP):