Adding iverilog simulation support

Examples/sram/logic/simulation/sram_bus_TB.do

@@ -3,7 +3,7 @@ vlog   -incr +libext+.v                    \
 			"../sram_bus.v"       \
 			"../sram_bus_TB.v"    \
 			"glbl.v"
-vsim -t 1ps -L simprims_ver -L unisims_ver -L xilinxcorelib_ver sram_bus_TB_v glbl
+vsim -t 1ps -L simprims_ver -L unisims_ver -L xilinxcorelib_ver sram_bus_TB glbl
 view wave
 #do wave.do
 add wave *

Examples/sram/logic/simulation/sram_bus_TIMING_TB.do

@@ -1,6 +1,6 @@
 vlib work
 vlog   -incr "../build/project.v" "../sram_bus_TB.v" "glbl.v"
-vsim -t 1ps -L simprims_ver -L unisims_ver -L xilinxcorelib_ver   sram_bus_TB_v glbl
+vsim -t 1ps -L simprims_ver -L unisims_ver -L xilinxcorelib_ver   sram_bus_TB glbl
 view wave
 #do wave.do
 add wave *

Examples/sram/logic/simulation/transcript

@@ -13,15 +13,15 @@
 # Model Technology ModelSim SE vlog 6.0d Compiler 2005.04 Apr 25 2005
 # -- Compiling module sram_bus
 # -- Compiling module glbl
-# -- Compiling module sram_bus_TB_v
+# -- Compiling module sram_bus_TB
 # ** Warning: glbl.v(5): 'glbl' already exists.
 # -- Compiling module glbl
 # 
 # Top level modules:
 # 	glbl
-# 	sram_bus_TB_v
-# vsim -L simprims_ver -L unisims_ver -L xilinxcorelib_ver -t 1ps sram_bus_TB_v glbl 
-# Loading work.sram_bus_TB_v
+# 	sram_bus_TB
+# vsim -L simprims_ver -L unisims_ver -L xilinxcorelib_ver -t 1ps sram_bus_TB glbl 
+# Loading work.sram_bus_TB
 # Loading work.sram_bus
 # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_ONE
 # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_ZERO
@@ -33,7 +33,6 @@
 # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_BUF
 # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_LUT3
 # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_INV
-# Refreshing /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_RAMB16_S2
 # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_RAMB16_S2
 # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_BPAD
 # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_IPAD
@@ -43,9 +42,9 @@
 # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_OBUF
 # Loading work.glbl
 # ** Warning: (vsim-3017) ../sram_bus_TB.v(21): [TFMPC] - Too few port connections. Expected 8, found 7.
-#         Region: /sram_bus_TB_v/uut
+#         Region: /sram_bus_TB/uut
 # ** Warning: (vsim-3015) ../sram_bus_TB.v(21): [PCDPC] - Port size (8 or 8) does not match connection size (1) for port 'sram_data'.
-#         Region: /sram_bus_TB_v/uut
+#         Region: /sram_bus_TB/uut
 # ** Warning: (vsim-3722) ../sram_bus_TB.v(21): [TFMPC] - Missing connection for port 'led'.
 # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.ffsrce
 # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.sffsrce
@@ -55,9 +54,4 @@
 # .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs
 # .main_pane.workspace
 # .main_pane.signals.interior.cs
-
-
-
-
-
-exit
+quit

Examples/sram/logic/simulation/work/_info

@@ -12,21 +12,32 @@ OE;L;6.0d;29
 r1
 31
 vsram_bus
-IYS7oKaz71LdIhQ>[[g2fo3
+IhWan4YkPClmK5z;GkOZUS2
 V7bnNHP1kz?3UaZfjPj4WE1
-w1273511584
+w1273543976
 F../build/project.v
 L0 37
 OE;L;6.0d;29
 r1
 31
-vsram_bus_TB_v
-IA=m;kT@<eh:`ekMlOPXX@0
-VQ[@Nfjd=de;Dc[[gj0bf41
-w1273511227
+vsram_bus_TB
+IeNSImUgW[X4l`QoUVUKI`3
+V<VFiY^801Z<UUJ?^z?JM20
+w1273543928
 F../sram_bus_TB.v
 L0 3
 OE;L;6.0d;29
 r1
 31
+nsram_bus_@t@b
+vsram_bus_TB_v
+IA=m;kT@<eh:`ekMlOPXX@0
+VQ[@Nfjd=de;Dc[[gj0bf41
+w1273541944
+F../sram_bus_TB.v
+L0 3
+OE;L;6.0d;29
+r1
+31
+o+libext+.v
 nsram_bus_@t@b_v