Adding iverilog simulation support

2025-04-21 12:27:27 +03:00 · 2010-05-12 09:36:30 -05:00
parent 23184f39dd
commit 079d8042f6
15 changed files with 72 additions and 30 deletions
--- a/Examples/sram/logic/simulation/work/_info
+++ b/Examples/sram/logic/simulation/work/_info
@@ -12,21 +12,32 @@ OE;L;6.0d;29
 r1
 31
 vsram_bus
-IYS7oKaz71LdIhQ>[[g2fo3
+IhWan4YkPClmK5z;GkOZUS2
 V7bnNHP1kz?3UaZfjPj4WE1
-w1273511584
+w1273543976
 F../build/project.v
 L0 37
 OE;L;6.0d;29
 r1
 31
-vsram_bus_TB_v
-IA=m;kT@<eh:`ekMlOPXX@0
-VQ[@Nfjd=de;Dc[[gj0bf41
-w1273511227
+vsram_bus_TB
+IeNSImUgW[X4l`QoUVUKI`3
+V<VFiY^801Z<UUJ?^z?JM20
+w1273543928
 F../sram_bus_TB.v
 L0 3
 OE;L;6.0d;29
 r1
 31
+nsram_bus_@t@b
+vsram_bus_TB_v
+IA=m;kT@<eh:`ekMlOPXX@0
+VQ[@Nfjd=de;Dc[[gj0bf41
+w1273541944
+F../sram_bus_TB.v
+L0 3
+OE;L;6.0d;29
+r1
+31
+o+libext+.v
 nsram_bus_@t@b_v
--- a/Examples/sram/logic/simulation/work/glbl/_primary.dat
+++ b/Examples/sram/logic/simulation/work/glbl/_primary.dat
--- a/Examples/sram/logic/simulation/work/sram_bus/_primary.dat
+++ b/Examples/sram/logic/simulation/work/sram_bus/_primary.dat
--- a/Examples/sram/logic/simulation/work/sram_bus/verilog.asm
+++ b/Examples/sram/logic/simulation/work/sram_bus/verilog.asm
--- a/Examples/sram/logic/simulation/work/sram_bus_@t@b_v/_primary.dat
+++ b/Examples/sram/logic/simulation/work/sram_bus_@t@b_v/_primary.dat
--- a/Examples/sram/logic/simulation/work/sram_bus_@t@b_v/verilog.asm
+++ b/Examples/sram/logic/simulation/work/sram_bus_@t@b_v/verilog.asm