Adding iverilog simulation support

Examples/blink/logic/Makefile

@@ -7,9 +7,18 @@ BGFLAGS         = -g TdoPin:PULLNONE -g DonePin:PULLUP \
 SIM_CMD         = vsim 
 SIM_COMP_SCRIPT = simulation/$(DESIGN)_TB.do
 SIMGEN_OPTIONS  = -p $(FPGA_ARCH) -lang $(LANGUAGE)
+IVERILOG        = iverilog
+
 SAKC_IP         = 192.168.254.101
 
 SRC             = $(DESIGN).v 
+
+SIM_SRC = $(DESIGN)_TB.v          \
+	sim/unisims/BUFG.v        \
+	sim/unisims/DCM.v         \
+	sim/unisims/FDDRRSE.v
+
+
  
 all:            bits
 
@@ -20,7 +29,7 @@ clean:
 	rm -f *.bit
 
 cleanall: clean
-	rm -rf build simulation/work simulation/transcript  simulation/vsim.wlf
+	rm -rf build simulation/work simulation/transcript  simulation/vsim.wlf simulation/blink_TB.vvp simulation/blink_TB.vcd
 
 bits:           $(DESIGN).bit
 
@@ -65,13 +74,18 @@ $(DESIGN).bit:  build/project_r.ncd build/project_r.twr
 	@mv -f build/project_r.bit $@
 
 build/project_r.v: build/project_r.ncd
-	cd build &&  netgen -sim -ofmt vhdl project_r.ncd -pcf project.pcf && ngd2ver project.ngd  -w project.v
+	cd build &&  netgen -sim -ofmt vhdl project_r.ncd -pcf project.pcf && ngd2ver projecsimulationt.ngd  -w project.v
 
-sim: 
+modelsim: 
 	cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do
 
 timesim: build/project_r.v
 	cd simulation; $(SIM_CMD) -do $(DESIGN)_TIMING_TB.do
 
+iversim:
+	$(IVERILOG) -o simulation/$(DESIGN)_TB.vvp $(VINCDIR) $(SRC) $(SIM_SRC) -s $(DESIGN)_TB_v
+	vvp simulation/$(DESIGN)_TB.vvp; mv $(DESIGN)_TB.vcd simulation/
+	gtkwave simulation/$(DESIGN)_TB.vcd&
+
 upload: $(DESIGN).bit
 	scp $(DESIGN).bit root@$(SAKC_IP): 

Examples/blink/logic/blink_TB.v

@@ -43,8 +43,12 @@ module blink_TB_v;
    end
 	 
 
-   initial begin: TEST_CASE	
+   initial begin: TEST_CASE
+     $dumpfile("blink_TB.vcd");
+     $dumpvars(-1, uut);
+	
      #10 -> reset_trigger;
+     #((PERIOD*DUTY_CYCLE)*100) $finish;
    end
 
 endmodule

Examples/sram/logic/Makefile

@@ -8,9 +8,21 @@ SIM_CMD         = /opt/cad/modeltech/bin/vsim
 SIM_COMP_SCRIPT = simulation/$(DESIGN)_TB.do
 SIMGEN_OPTIONS  = -p $(FPGA_ARCH) -lang $(LANGUAGE)
 SAKC_IP         = 192.168.254.101
+IVERILOG        = iverilog
+XILINXCADROOT   = /opt/cad/Xilinx/verilog/src
+#XILINXCADROOT   = /opt/cad/modeltech/xilinx/verilog/
+
 
 SRC             = sram_bus.v 
- 
+
+SIM_SRC = $(DESIGN)_TB.v          \
+#	sim/unisims/BUFG.v        \
+#	sim/unisims/DCM.v         \
+#	sim/unisims/FDDRRSE.v     \
+#        glbl.v
+#	sim/unisims/RAMB16_S2_S9.v
+
+
 all:            bits
 
 remake:         clean-build all
@@ -70,11 +82,17 @@ $(DESIGN).bit:  build/project_r.ncd build/project_r.twr
 build/project_r.v: build/project_r.ncd
 	cd build &&  netgen -sim -ofmt vhdl project_r.ncd -pcf project.pcf && ngd2ver project.ngd  -w project.v
 
-sim: 
+modelsim: 
 	cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do
 
 timesim: build/project_r.v
 	cd simulation; $(SIM_CMD) -do $(DESIGN)_TIMING_TB.do
 
+iversim:
+	$(IVERILOG) -Wall -y $(XILINXCADROOT)/unisims  -y $(XILINXCADROOT)/XilinxCoreLib -o simulation/$(DESIGN)_TB.vvp $(VINCDIR) $(SRC) $(SIM_SRC) -s $(DESIGN)_TB
+#	$(IVERILOG) -Wall -y $(XILINXCADROOT)/unisims  -y $(XILINXCADROOT)/XilinxCoreLib -o simulation/$(DESIGN)_TB.vvp $(VINCDIR) build/project.v $(SIM_SRC) -s $(DESIGN)_TB
+	vvp simulation/$(DESIGN)_TB.vvp; mv $(DESIGN)_TB.vcd simulation/
+	gtkwave simulation/$(DESIGN)_TB.vcd&
+
 upload: $(DESIGN).bit
 	scp $(DESIGN).bit root@$(SAKC_IP): 

Examples/sram/logic/simulation/sram_bus_TB.do

@@ -3,7 +3,7 @@ vlog   -incr +libext+.v                    \
 			"../sram_bus.v"       \
 			"../sram_bus_TB.v"    \
 			"glbl.v"
-vsim -t 1ps -L simprims_ver -L unisims_ver -L xilinxcorelib_ver sram_bus_TB_v glbl
+vsim -t 1ps -L simprims_ver -L unisims_ver -L xilinxcorelib_ver sram_bus_TB glbl
 view wave
 #do wave.do
 add wave *

Examples/sram/logic/simulation/sram_bus_TIMING_TB.do

@@ -1,6 +1,6 @@
 vlib work
 vlog   -incr "../build/project.v" "../sram_bus_TB.v" "glbl.v"
-vsim -t 1ps -L simprims_ver -L unisims_ver -L xilinxcorelib_ver   sram_bus_TB_v glbl
+vsim -t 1ps -L simprims_ver -L unisims_ver -L xilinxcorelib_ver   sram_bus_TB glbl
 view wave
 #do wave.do
 add wave *

Examples/sram/logic/simulation/transcript

@@ -13,15 +13,15 @@
 # Model Technology ModelSim SE vlog 6.0d Compiler 2005.04 Apr 25 2005
 # -- Compiling module sram_bus
 # -- Compiling module glbl
-# -- Compiling module sram_bus_TB_v
+# -- Compiling module sram_bus_TB
 # ** Warning: glbl.v(5): 'glbl' already exists.
 # -- Compiling module glbl
 # 
 # Top level modules:
 # 	glbl
-# 	sram_bus_TB_v
+# 	sram_bus_TB
-# vsim -L simprims_ver -L unisims_ver -L xilinxcorelib_ver -t 1ps sram_bus_TB_v glbl 
+# vsim -L simprims_ver -L unisims_ver -L xilinxcorelib_ver -t 1ps sram_bus_TB glbl 
-# Loading work.sram_bus_TB_v
+# Loading work.sram_bus_TB
 # Loading work.sram_bus
 # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_ONE
 # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_ZERO
@@ -33,7 +33,6 @@
 # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_BUF
 # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_LUT3
 # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_INV
-# Refreshing /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_RAMB16_S2
 # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_RAMB16_S2
 # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_BPAD
 # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_IPAD
@@ -43,9 +42,9 @@
 # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_OBUF
 # Loading work.glbl
 # ** Warning: (vsim-3017) ../sram_bus_TB.v(21): [TFMPC] - Too few port connections. Expected 8, found 7.
-#         Region: /sram_bus_TB_v/uut
+#         Region: /sram_bus_TB/uut
 # ** Warning: (vsim-3015) ../sram_bus_TB.v(21): [PCDPC] - Port size (8 or 8) does not match connection size (1) for port 'sram_data'.
-#         Region: /sram_bus_TB_v/uut
+#         Region: /sram_bus_TB/uut
 # ** Warning: (vsim-3722) ../sram_bus_TB.v(21): [TFMPC] - Missing connection for port 'led'.
 # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.ffsrce
 # Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.sffsrce
@@ -55,9 +54,4 @@
 # .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs
 # .main_pane.workspace
 # .main_pane.signals.interior.cs
-
+quit
-
-
-
-
-exit

Examples/sram/logic/simulation/work/_info

@@ -12,21 +12,32 @@ OE;L;6.0d;29
 r1
 31
 vsram_bus
-IYS7oKaz71LdIhQ>[[g2fo3
+IhWan4YkPClmK5z;GkOZUS2
 V7bnNHP1kz?3UaZfjPj4WE1
-w1273511584
+w1273543976
 F../build/project.v
 L0 37
 OE;L;6.0d;29
 r1
 31
-vsram_bus_TB_v
+vsram_bus_TB
-IA=m;kT@<eh:`ekMlOPXX@0
+IeNSImUgW[X4l`QoUVUKI`3
-VQ[@Nfjd=de;Dc[[gj0bf41
+V<VFiY^801Z<UUJ?^z?JM20
-w1273511227
+w1273543928
 F../sram_bus_TB.v
 L0 3
 OE;L;6.0d;29
 r1
 31
+nsram_bus_@t@b
+vsram_bus_TB_v
+IA=m;kT@<eh:`ekMlOPXX@0
+VQ[@Nfjd=de;Dc[[gj0bf41
+w1273541944
+F../sram_bus_TB.v
+L0 3
+OE;L;6.0d;29
+r1
+31
+o+libext+.v
 nsram_bus_@t@b_v

Examples/sram/logic/sram_bus.v

@@ -2,7 +2,8 @@
 module sram_bus(clk, sram_data, addr, nwe, ncs, noe, reset, led);
   parameter     B = (7);
 
-  input            clk, addr, nwe, ncs, noe, reset;
+  input            clk, nwe, ncs, noe, reset;
+  input [12:0]     addr;
   inout [B:0]      sram_data;
   output           led;
 
@@ -12,7 +13,7 @@ module sram_bus(clk, sram_data, addr, nwe, ncs, noe, reset, led);
   reg    [B:0] buffer_data;  
 
   // interfaz fpga signals
-  wire   [12:0] addr;
+//  wire   [12:0] addr;
 	
   // bram interfaz signals
   reg    we;

Examples/sram/logic/sram_bus_TB.v

@@ -1,6 +1,6 @@
 `timescale 1ns / 1ps
 
-module sram_bus_TB_v;
+module sram_bus_TB;
 
    // inputs
    reg clk;