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Code

fixed logic for Evalfit peripheral

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This commit is contained in:
César Pedraza 2010-10-12 10:21:30 -05:00
parent c48feff62c
commit 5fbd9db02f
2 changed files with 30 additions and 30 deletions
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52
Examples/ehw4/logic/evalfit_peripheral.vhd
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@ -3,15 +3,15 @@
-- Evalua un arbol de 5 pentarboles, por ahora es valido hasta para *** 14 variables *** -- Evalua un arbol de 5 pentarboles, por ahora es valido hasta para *** 14 variables ***
-- Funciona hasta con 14 vars. -- Funciona hasta con 14 vars.
-- mapa: -- mapa:
-- 0 - 0x3F Cromosoma -- 0 - 0x3F Cromosoma (cada uno con 64-bit)
-- 0x40 - 0x13F Objetivo. 16384 bits. Se empieza por el bit 0 MSB. -- 0x40 - 0x13F Objetivo. 16384 bits. Se empieza por el bit 0 MSB.
-- Cromosoma en memoria -- Mapa de cromosoma:
-- bit bit Contenido -- bit bit Contenido
-- 28 a 31 Nivel del arbol -- 28 a 31 Nivel del arbol
-- 32 a 47 LUT o tabla del arbol -- 32 a 47 LUT o tabla del arbol LUT(32)MSB, LUT(47)LSB,
-- 48 a 63 Variables de entrada del arbol (4 bits por variable) -- 48 a 63 Variables de entrada del arbol (4 bits por variable) 48-51 MSB, 60-63 LSB
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
@ -25,12 +25,12 @@ entity evalfit_peripheral is
Port ( clk, reset, habilita: in STD_LOGIC; Port ( clk, reset, habilita: in STD_LOGIC;
maxcombs : in STD_LOGIC_VECTOR (0 to 15); maxcombs : in STD_LOGIC_VECTOR (0 to 15);
nivel_max : in STD_LOGIC_VECTOR (0 to 3); nivel_max : in STD_LOGIC_VECTOR (0 to 3);
peripheral_mem_in : in STD_LOGIC_VECTOR (0 to 63); peripheral_mem_in : in STD_LOGIC_VECTOR (0 to 63);
peripheral_mem_en : out std_logic; peripheral_mem_en : out std_logic;
peripheral_mem_out : out STD_LOGIC_VECTOR (0 to 63); peripheral_mem_out: out STD_LOGIC_VECTOR (0 to 63);
peripheral_mem_we : out STD_LOGIC; peripheral_mem_we : out STD_LOGIC;
peripheral_mem_addr : out STD_LOGIC_VECTOR (0 to 8); peripheral_mem_addr: out STD_LOGIC_VECTOR (0 to 8);
evalfit3_estado : out std_logic_vector(0 to 7); evalfit3_estado : out std_logic_vector(0 to 15);
errores : out STD_LOGIC_VECTOR (0 to 15); errores : out STD_LOGIC_VECTOR (0 to 15);
fin_ack : out std_logic; fin_ack : out std_logic;
reg0_s : out STD_LOGIC_VECTOR (0 to 31); reg0_s : out STD_LOGIC_VECTOR (0 to 31);
@ -54,7 +54,7 @@ begin
when "0101" => return ent(10); when "0101" => return ent(10);
when "0110" => return ent(9); when "0110" => return ent(9);
when "0111" => return ent(8); when "0111" => return ent(8);
when "1000" => return ent(7); when "1000" => return ent(7);
when "1001" => return ent(6); when "1001" => return ent(6);
when "1010" => return ent(5); when "1010" => return ent(5);
when "1011" => return ent(4); when "1011" => return ent(4);
@ -95,7 +95,7 @@ signal ep, es: estado;
signal nivel, nivel_sig, nivel_reg: std_logic_vector(0 to 3); signal nivel, nivel_sig, nivel_reg: std_logic_vector(0 to 3);
signal c1, c1_sig, c2, c2_sig, c3, c3_sig, c4, c4_sig: std_logic_vector(0 to 1); signal c1, c1_sig, c2, c2_sig, c3, c3_sig, c4, c4_sig: std_logic_vector(0 to 1);
signal conta, conta_sig, conta2, conta2_sig: std_logic_vector(0 to 15); signal conta, conta_sig, conta2, conta2_sig: std_logic_vector(0 to 15);
signal estado_evalf3, estado_evalf3_sig: std_logic_vector(0 to 7); signal estado_evalf3, estado_evalf3_sig: std_logic_vector(0 to 15);
signal peripheral_mem_addr_aux, peripheral_mem_addr_sig, peripheral_mem_addr_crom_sig,peripheral_mem_addr_crom : STD_LOGIC_VECTOR (0 to 8); signal peripheral_mem_addr_aux, peripheral_mem_addr_sig, peripheral_mem_addr_crom_sig,peripheral_mem_addr_crom : STD_LOGIC_VECTOR (0 to 8);
begin begin
@ -132,18 +132,20 @@ peripheral_mem_we <= '0';
peripheral_mem_en <= '0'; peripheral_mem_en <= '0';
errores_sig <= errores_aux; errores_sig <= errores_aux;
nivel_sig <= nivel_reg; nivel_sig <= nivel_reg;
estado_evalf3_sig <= x"FF"; estado_evalf3_sig <= x"FFFF";
case ep is case ep is
when reset1 => --poner la memoria a 0000 when reset1 => --poner la memoria a 0000
WE_n2_sig <= "1111"; WE_n2_sig <= "1111";
WE_n3_sig <= "1111"; WE_n3_sig <= "1111";
WE_n4_sig <= "1111"; WE_n4_sig <= "1111";
conta2_sig <= (others => '0'); conta2_sig <= (others => '0');
estado_evalf3_sig <= x"0001";
es <= reset2; es <= reset2;
when reset2 => when reset2 =>
DI_n2 <= "0000"; DI_n2 <= "0000";
DI_n3 <= "0000"; DI_n3 <= "0000";
DI_n4 <= "0000"; DI_n4 <= "0000";
estado_evalf3_sig <= x"0002";
if(conta2 = maxcombs)then if(conta2 = maxcombs)then
WE_n2_sig <= "0000"; WE_n2_sig <= "0000";
WE_n3_sig <= "0000"; WE_n3_sig <= "0000";
@ -173,7 +175,7 @@ case ep is
es <= proceso; es <= proceso;
peripheral_mem_en <= '1'; peripheral_mem_en <= '1';
end if; end if;
estado_evalf3_sig <= x"01"; estado_evalf3_sig <= x"0003";
when proceso => when proceso =>
peripheral_mem_en <= '1'; peripheral_mem_en <= '1';
@ -206,14 +208,14 @@ case ep is
peripheral_mem_addr_sig <= peripheral_mem_addr_aux + 1; peripheral_mem_addr_sig <= peripheral_mem_addr_aux + 1;
peripheral_mem_addr_crom_sig <= peripheral_mem_addr_aux + 1; peripheral_mem_addr_crom_sig <= peripheral_mem_addr_aux + 1;
nivel_sig <= nivel; nivel_sig <= nivel;
estado_evalf3_sig <= x"02"; estado_evalf3_sig <= peripheral_mem_in(48 to 63);--x"FFE" & nivel;----x"02";
when n1 => when n1 =>
peripheral_mem_en <= '1'; peripheral_mem_en <= '1';
c1_sig <= c1 + 1; c1_sig <= c1 + 1;
peripheral_mem_addr_sig <= peripheral_mem_addr_aux; peripheral_mem_addr_sig <= peripheral_mem_addr_aux;
es <= proceso; es <= proceso;
estado_evalf3_sig <= x"03"; estado_evalf3_sig <= x"0004";
when n2 => when n2 =>
WE_n2_sig(conv_integer(c2)) <= '1'; WE_n2_sig(conv_integer(c2)) <= '1';
@ -222,7 +224,7 @@ case ep is
peripheral_mem_addr_sig <= "001000000" + ('0' & conta(2 to 9));-- esto es para que evalue el pentarbol y guarde en memoria la salida peripheral_mem_addr_sig <= "001000000" + ('0' & conta(2 to 9));-- esto es para que evalue el pentarbol y guarde en memoria la salida
es <= precuenta; es <= precuenta;
conta2_sig <= (others => '0'); conta2_sig <= (others => '0');
estado_evalf3_sig <= x"04"; estado_evalf3_sig <= x"0005";
when n3 => when n3 =>
WE_n3_sig(conv_integer(c3)) <= '1'; WE_n3_sig(conv_integer(c3)) <= '1';
@ -231,7 +233,7 @@ case ep is
peripheral_mem_addr_sig <= "001000000" + ('0' & conta(2 to 9));-- peripheral_mem_addr_sig <= "001000000" + ('0' & conta(2 to 9));--
es <= precuenta; es <= precuenta;
conta2_sig <= (others => '0'); conta2_sig <= (others => '0');
estado_evalf3_sig <= x"05"; estado_evalf3_sig <= x"0006";
when n4 => when n4 =>
WE_n4_sig(conv_integer(c4)) <= '1'; WE_n4_sig(conv_integer(c4)) <= '1';
@ -240,7 +242,7 @@ case ep is
peripheral_mem_addr_sig <= "001000000" + ('0' & conta(2 to 9));-- peripheral_mem_addr_sig <= "001000000" + ('0' & conta(2 to 9));--
es <= precuenta; es <= precuenta;
conta2_sig <= (others => '0'); conta2_sig <= (others => '0');
estado_evalf3_sig <= x"06"; estado_evalf3_sig <= x"0007";
when precuenta => when precuenta =>
WE_n2_sig <= WE_n2; WE_n2_sig <= WE_n2;
@ -254,7 +256,7 @@ case ep is
conta_sig <= conta; conta_sig <= conta;
conta2_sig <= conta + 1; conta2_sig <= conta + 1;
es <= cuenta; es <= cuenta;
estado_evalf3_sig <= x"07"; estado_evalf3_sig <= x"0008";
when cuenta => when cuenta =>
DI_n2(conv_integer(c2)) <= salida_nivel(2); DI_n2(conv_integer(c2)) <= salida_nivel(2);
@ -292,7 +294,7 @@ case ep is
errores_sig <= errores_aux; errores_sig <= errores_aux;
end if; end if;
estado_evalf3_sig <= x"08"; estado_evalf3_sig <= x"0009";
when final => when final =>
if(nivel_reg = "0010")then if(nivel_reg = "0010")then
@ -305,7 +307,7 @@ case ep is
peripheral_mem_en <= '1'; peripheral_mem_en <= '1';
peripheral_mem_addr_sig <= peripheral_mem_addr_crom; peripheral_mem_addr_sig <= peripheral_mem_addr_crom;
es <= proceso; es <= proceso;
estado_evalf3_sig <= x"09"; estado_evalf3_sig <= x"000A";
when final2 => when final2 =>
if(habilita = '1') then if(habilita = '1') then
@ -314,7 +316,7 @@ case ep is
es <= inicio; es <= inicio;
end if; end if;
fin_ack_sig <= '1'; fin_ack_sig <= '1';
estado_evalf3_sig <= x"0A"; estado_evalf3_sig <= x"000B";
when others => es <= inicio; when others => es <= inicio;
end case; end case;
@ -346,7 +348,7 @@ begin
peripheral_mem_addr_crom <= "000000000"; peripheral_mem_addr_crom <= "000000000";
errores_aux <= (others => '0'); errores_aux <= (others => '0');
nivel_reg <= "0000"; nivel_reg <= "0000";
estado_evalf3 <= x"00"; estado_evalf3 <= x"0000";
elsif(rising_edge(clk))then elsif(rising_edge(clk))then
ep <= es; ep <= es;
c1 <= c1_sig; c1 <= c1_sig;

8
Examples/ehw4/logic/reg_bank.v
View File

@ -29,12 +29,11 @@ module reg_bank(clk, reset, en, we, wdBus, rdBus, address, reg0, reg1, reg2, reg
// Read control // Read control
always @(posedge clk) always @(posedge clk)
if(reset) if(reset)
rdBus = 8'h00; rdBus = 8'h00;
else begin else begin
rdBus = reg_bank[address]; rdBus = reg_bank[address];
end end
// Store Inputs // Store Inputs
always @(posedge clk) always @(posedge clk)
begin begin
@ -67,7 +66,7 @@ module reg_bank(clk, reset, en, we, wdBus, rdBus, address, reg0, reg1, reg2, reg
reg_bank[20] = error[7:0]; reg_bank[20] = error[7:0];
reg_bank[21] = error[15:8]; reg_bank[21] = error[15:8];
reg_bank[22] = { 4'b0, status}; reg_bank[22] = {4'b0, status};
// reg_bank[23] = regMT[7:0]; // reg_bank[23] = regMT[7:0];
// reg_bank[24] = regMT[15:8]; // reg_bank[24] = regMT[15:8];
@ -76,7 +75,6 @@ module reg_bank(clk, reset, en, we, wdBus, rdBus, address, reg0, reg1, reg2, reg
end end
end end
assign max_com[7:0] = reg_bank[26]; assign max_com[7:0] = reg_bank[26];
assign max_com[15:8] = reg_bank[27]; assign max_com[15:8] = reg_bank[27];
assign max_lev = reg_bank[28]; assign max_lev = reg_bank[28];