Adding post route simulation to FPGA examples

Examples/sram/logic/simulation/glbl.v

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+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.11.156.1 2007/03/09 18:12:55 patrickp Exp $
+
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+    wire GSR;
+    wire GTS;
+    wire PRLD;
+
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (weak1, weak0) GSR = GSR_int;
+    assign (weak1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule

Examples/sram/logic/simulation/sram_bus_TB.do

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+vlib work
+vlog   -incr +libext+.v                    \
+			"../sram_bus.v"       \
+			"../sram_bus_TB.v"    \
+			"glbl.v"
+vsim -t 1ps -L simprims_ver -L unisims_ver -L xilinxcorelib_ver sram_bus_TB_v glbl
+view wave
+#do wave.do
+add wave *
+view structure
+view signals
+run 5us

Examples/sram/logic/simulation/sram_bus_TIMING_TB.do

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+vlib work
+vlog   -incr "../build/project.v" "../sram_bus_TB.v" "glbl.v"
+vsim -t 1ps -L simprims_ver -L unisims_ver -L xilinxcorelib_ver   sram_bus_TB_v glbl
+view wave
+#do wave.do
+add wave *
+view structure
+view signals
+run 5us

Examples/sram/logic/simulation/transcript

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+# //  ModelSim SE 6.0d Apr 25 2005 Linux 2.6.32-22-generic
+# //
+# //  Copyright Mentor Graphics Corporation 2005
+# //              All Rights Reserved.
+# //
+# //  THIS WORK CONTAINS TRADE SECRET AND 
+# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
+# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
+# //  AND IS SUBJECT TO LICENSE TERMS.
+# //
+# do sram_bus_TIMING_TB.do 
+# ** Warning: (vlib-34) Library already exists at "work".
+# Model Technology ModelSim SE vlog 6.0d Compiler 2005.04 Apr 25 2005
+# -- Compiling module sram_bus
+# -- Compiling module glbl
+# -- Compiling module sram_bus_TB_v
+# ** Warning: glbl.v(5): 'glbl' already exists.
+# -- Compiling module glbl
+# 
+# Top level modules:
+# 	glbl
+# 	sram_bus_TB_v
+# vsim -L simprims_ver -L unisims_ver -L xilinxcorelib_ver -t 1ps sram_bus_TB_v glbl 
+# Loading work.sram_bus_TB_v
+# Loading work.sram_bus
+# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_ONE
+# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_ZERO
+# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_FF
+# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_SFF
+# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_MUX2
+# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_XOR2
+# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_LUT2
+# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_BUF
+# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_LUT3
+# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_INV
+# Refreshing /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_RAMB16_S2
+# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_RAMB16_S2
+# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_BPAD
+# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_IPAD
+# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_OPAD
+# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_CKBUF
+# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_OBUFT
+# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.X_OBUF
+# Loading work.glbl
+# ** Warning: (vsim-3017) ../sram_bus_TB.v(21): [TFMPC] - Too few port connections. Expected 8, found 7.
+#         Region: /sram_bus_TB_v/uut
+# ** Warning: (vsim-3015) ../sram_bus_TB.v(21): [PCDPC] - Port size (8 or 8) does not match connection size (1) for port 'sram_data'.
+#         Region: /sram_bus_TB_v/uut
+# ** Warning: (vsim-3722) ../sram_bus_TB.v(21): [TFMPC] - Missing connection for port 'led'.
+# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.ffsrce
+# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.sffsrce
+# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.mux
+# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.x_lut2_mux4
+# Loading /opt/cad/modeltech/xilinx/verilog/simprims_ver.x_lut3_mux4
+# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs
+# .main_pane.workspace
+# .main_pane.signals.interior.cs
+
+
+
+
+
+exit

Examples/sram/logic/simulation/wave.do

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+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic -radix hexadecimal /sram_bus_TB_v/clk
+add wave -noupdate -format Literal -radix hexadecimal /sram_bus_TB_v/addr
+add wave -noupdate -format Logic -radix hexadecimal /sram_bus_TB_v/nwe
+add wave -noupdate -format Logic -radix hexadecimal /sram_bus_TB_v/ncs
+add wave -noupdate -format Logic -radix hexadecimal /sram_bus_TB_v/noe
+add wave -noupdate -format Logic -radix hexadecimal /sram_bus_TB_v/reset
+add wave -noupdate -format Logic -radix hexadecimal /sram_bus_TB_v/led
+add wave -noupdate -format Literal -radix hexadecimal {/sram_bus_TB_v/sram_data$inout$reg}
+add wave -noupdate -format Logic -radix hexadecimal /sram_bus_TB_v/sram_data
+add wave -noupdate -format Literal -radix hexadecimal /sram_bus_TB_v/data_tx
+add wave -noupdate -format Logic -radix hexadecimal /glbl/GSR
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {154070 ps} 0}
+configure wave -namecolwidth 323
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {0 ps} {656250 ps}

Examples/sram/logic/simulation/work/_info

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+m255
+13
+cModel Technology
+d/home/cain/Embedded/ingenic/sakc/nn-usb-fpga/Examples/sram/logic/simulation
+vglbl
+IT?5S;>bN`@zG_25]R_4A33
+VnN]4Gon>inod6>M^M2[SV1
+w1273510321
+Fglbl.v
+L0 5
+OE;L;6.0d;29
+r1
+31
+vsram_bus
+IYS7oKaz71LdIhQ>[[g2fo3
+V7bnNHP1kz?3UaZfjPj4WE1
+w1273511584
+F../build/project.v
+L0 37
+OE;L;6.0d;29
+r1
+31
+vsram_bus_TB_v
+IA=m;kT@<eh:`ekMlOPXX@0
+VQ[@Nfjd=de;Dc[[gj0bf41
+w1273511227
+F../sram_bus_TB.v
+L0 3
+OE;L;6.0d;29
+r1
+31
+nsram_bus_@t@b_v

Examples/sram/logic/simulation/work/glbl/_primary.vhd

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+library verilog;
+use verilog.vl_types.all;
+entity glbl is
+    generic(
+        ROC_WIDTH       : integer := 100000;
+        TOC_WIDTH       : integer := 0
+    );
+end glbl;

Examples/sram/logic/simulation/work/sram_bus/_primary.vhd

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+library verilog;
+use verilog.vl_types.all;
+entity sram_bus is
+    port(
+        clk             : in     vl_logic;
+        reset           : in     vl_logic;
+        ncs             : in     vl_logic;
+        noe             : in     vl_logic;
+        nwe             : in     vl_logic;
+        led             : out    vl_logic;
+        sram_data       : inout  vl_logic_vector(7 downto 0);
+        addr            : in     vl_logic_vector(12 downto 0)
+    );
+end sram_bus;

Examples/sram/logic/simulation/work/sram_bus_@t@b_v/_primary.vhd

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+library verilog;
+use verilog.vl_types.all;
+entity sram_bus_TB_v is
+    generic(
+        PERIOD          : integer := 20;
+        DUTY_CYCLE      : real    := 0.500000;
+        OFFSET          : integer := 0;
+        TSET            : integer := 3;
+        THLD            : integer := 3;
+        NWS             : integer := 3;
+        CAM_OFF         : integer := 4000
+    );
+end sram_bus_TB_v;