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Code

SRAM fixed to 4 BRAM (8KB)

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This commit is contained in:
afc 2010-03-18 08:18:01 -05:00
parent 710061371d
commit 7a27846dca
1 changed files with 13 additions and 7 deletions
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20
Examples/sram/logic/sram_bus.v
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@ -6,9 +6,6 @@ module sram_bus(clk, sram_data, addr, nwe, ncs, noe, reset, led);
inout [B:0] sram_data;
output led;
// Internal conection
wire led;
// synchronize signals
reg sncs, snwe;
reg [12:0] buffer_addr;
@ -59,13 +56,22 @@ module sram_bus(clk, sram_data, addr, nwe, ncs, noe, reset, led);
endcase
end
RAMB16_S18 ba0( .CLK(~clk), .EN(1'b1), .SSR(1'b0), .ADDR(buffer_addr),
.WE(we), .DIP(2'b00), .DI(wdBus), .DO(rdBus) );
RAMB16_S2 ba0( .CLK(~clk), .EN(1'b1), .SSR(1'b0), .ADDR(buffer_addr),
.WE(we), .DI(wdBus[1:0]), .DO(rdBus[1:0]) );
reg [32:0] counter;
RAMB16_S2 ba1( .CLK(~clk), .EN(1'b1), .SSR(1'b0), .ADDR(buffer_addr),
.WE(we), .DI(wdBus[3:2]), .DO(rdBus[3:2]) );
RAMB16_S2 ba2( .CLK(~clk), .EN(1'b1), .SSR(1'b0), .ADDR(buffer_addr),
.WE(we), .DI(wdBus[5:4]), .DO(rdBus[5:4]) );
RAMB16_S2 ba3( .CLK(~clk), .EN(1'b1), .SSR(1'b0), .ADDR(buffer_addr),
.WE(we), .DI(wdBus[7:6]), .DO(rdBus[7:6]) );
reg [24:0] counter;
always @(posedge clk) begin
if (reset)
counter <= {32{1'b0}};
counter <= {25{1'b0}};
else
counter <= counter + 1;
end