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Fix issues form previous commit...
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@ -1,26 +0,0 @@
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/*
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* linux/include/asm-mips/jzsoc.h
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*
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* Ingenic's JZXXXX SoC common include.
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*
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* Copyright (C) 2006 - 2008 Ingenic Semiconductor Inc.
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*
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* Author: <jlwei@ingenic.cn>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_JZSOC_H__
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#define __ASM_JZSOC_H__
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/*
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* SoC include
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*/
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#ifdef CONFIG_SOC_JZ4740
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#include <asm/mach-jz4740/jz4740.h>
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#endif
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#endif /* __ASM_JZSOC_H__ */
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@ -59,7 +59,7 @@
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*/
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*/
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#define MSC_WP_PIN GPIO_SD_WP
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#define MSC_WP_PIN GPIO_SD_WP
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#define MSC_HOTPLUG_PIN GPIO_SD_CD_N
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#define MSC_HOTPLUG_PIN GPIO_SD_CD_N
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#define MSC_HOTPLUG_IRQ (IRQ_GPIO_0 + GPIO_SD_CD_N)
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#define MSC_HOTPLUG_IRQ (JZ_IRQ_GPIO(GPIO_SD_CD_N))
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#define __msc_init_io() \
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#define __msc_init_io() \
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do { \
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do { \
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@ -1,15 +1,7 @@
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#ifndef __JZ4740_IRQ_H__
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#ifndef __JZ4740_IRQ_H__
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#define __JZ4740_IRQ_H__
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#define __JZ4740_IRQ_H__
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/*
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* JZ4740 irqs.
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*
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* Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#define MIPS_CPU_IRQ_BASE 0
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#define JZ_IRQ_BASE 8
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#define JZ_IRQ_BASE 8
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// 1st-level interrupts
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// 1st-level interrupts
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@ -39,10 +31,9 @@
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/* 2nd-level interrupts */
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/* 2nd-level interrupts */
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#define JZ_IRQ_DMA(x) ((x) + JZ_IRQ(32)) /* 32 to 37 for DMAC channel 0 to 5 */
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#define JZ_IRQ_DMA(x) ((x) + JZ_IRQ(32)) /* 32 to 37 for DMAC channel 0 to 5 */
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#define JZ_IRQ_GPIO_0 JZ_IRQ(48) /* 48 to 175 for GPIO pin 0 to 127 */
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#define JZ_IRQ_INTC_GPIO(x) (JZ_IRQ_GPIO0 - (x))
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#define JZ_IRQ_INTC_GPIO(x) (JZ_IRQ_GPIO0 - (x))
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#define JZ_IRQ_GPIO(x) ((x) + JZ_IRQ(48)
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#define JZ_IRQ_GPIO(x) (JZ_IRQ(48) + (x))
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#define NR_IRQS (JZ_IRQ_GPIO(127) + 1)
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#define NR_IRQS (JZ_IRQ_GPIO(127) + 1)
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