mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-24 19:41:53 +02:00
add support for the qi_lb60 support (thanks to the work of Xiang Fu) -> LCM/LCD and MMC are supported and working
This commit is contained in:
Mirko Vogt
Xiangfu Liu
parent
a513356b50
commit
29d473a66e
383
target/linux/xburst/patches-2.6.25/010-add-qi_lb60.patch
Normal file
383
target/linux/xburst/patches-2.6.25/010-add-qi_lb60.patch
Normal file
@ -0,0 +1,383 @@
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diff -ruN linux-2.6.25.20.owrt.qi/arch/mips/jz4740/board-qi_lb60.c linux-2.6.25.20.owrt.qi.mod/arch/mips/jz4740/board-qi_lb60.c
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--- linux-2.6.25.20.owrt.qi/arch/mips/jz4740/board-qi_lb60.c 1970-01-01 01:00:00.000000000 +0100
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+++ linux-2.6.25.20.owrt.qi.mod/arch/mips/jz4740/board-qi_lb60.c 2009-08-06 22:20:19.000000000 +0200
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@@ -0,0 +1,110 @@
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+/*
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+ * linux/arch/mips/jz4740/board-qi_lb60.c
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+ *
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+ * QI_LB60 setup routines.
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+ *
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+ * Copyright (c) 2009 Qi Hardware inc.,
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+ * Author: Xiangfu Liu <xiangfu@qi-hardware.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 3 as
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+ * published by the Free Software Foundation.
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+ */
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+
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+#include <linux/init.h>
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+#include <linux/sched.h>
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+#include <linux/ioport.h>
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+#include <linux/mm.h>
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+#include <linux/console.h>
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+#include <linux/delay.h>
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+
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+#include <asm/cpu.h>
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+#include <asm/bootinfo.h>
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+#include <asm/mipsregs.h>
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+#include <asm/reboot.h>
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+
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+#include <asm/jzsoc.h>
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+
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+extern void (*jz_timer_callback)(void);
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+
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+static void dancing(void)
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+{
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+ static unsigned int count = 0;
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+
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+ count ++;
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+ count &= 1;
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+ if (count)
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+ __gpio_set_pin(GPIO_LED_EN);
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+ else
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+ __gpio_clear_pin(GPIO_LED_EN);
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+}
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+
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+static void pi_timer_callback(void)
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+{
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+ static unsigned long count = 0;
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+
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+ if ((++count) % 50 == 0) {
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+ dancing();
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+ count = 0;
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+ }
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+}
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+
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+static void __init board_cpm_setup(void)
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+{
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+ /* Stop unused module clocks here.
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+ * We have started all module clocks at arch/mips/jz4740/setup.c.
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+ */
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+}
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+
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+static void __init board_gpio_setup(void)
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+{
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+ /*
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+ * Most of the GPIO pins should have been initialized by the boot-loader
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+ */
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+
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+ /*
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+ * Initialize MSC pins
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+ */
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+ /* __gpio_as_msc(); */
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+
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+ /*
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+ * Initialize LCD pins
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+ */
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+ /* __gpio_as_lcd_18bit(); */
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+
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+ /*
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+ * Initialize SSI pins
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+ */
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+ /* __gpio_as_ssi(); */
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+
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+ /*
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+ * Initialize I2C pins
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+ */
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+ /* __gpio_as_i2c(); */
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+
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+ /*
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+ * Initialize Other pins
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+ */
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+ __gpio_as_output(GPIO_SD_VCC_EN_N);
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+ __gpio_disable_pull(GPIO_SD_VCC_EN_N);
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+ __gpio_clear_pin(GPIO_SD_VCC_EN_N);
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+
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+ __gpio_as_input(GPIO_SD_CD_N);
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+ __gpio_disable_pull(GPIO_SD_CD_N);
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+
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+ __gpio_as_input(GPIO_SD_WP);
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+ __gpio_disable_pull(GPIO_SD_WP);
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+
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+ __gpio_as_input(GPIO_DC_DETE_N);
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+ __gpio_as_input(GPIO_CHARG_STAT_N);
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+}
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+
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+void __init jz_board_setup(void)
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+{
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+ printk("Qi Hardware JZ4740 QI_LB60 setup\n");
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+
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+ board_cpm_setup();
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+ board_gpio_setup();
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+
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+ jz_timer_callback = pi_timer_callback;
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+}
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diff -ruN linux-2.6.25.20.owrt.qi/arch/mips/jz4740/Makefile linux-2.6.25.20.owrt.qi.mod/arch/mips/jz4740/Makefile
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--- linux-2.6.25.20.owrt.qi/arch/mips/jz4740/Makefile 2009-08-05 03:02:12.000000000 +0200
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+++ linux-2.6.25.20.owrt.qi.mod/arch/mips/jz4740/Makefile 2009-08-06 19:01:25.000000000 +0200
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@@ -16,6 +16,7 @@
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obj-$(CONFIG_JZ4740_LYRA) += board-lyra.o
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obj-$(CONFIG_JZ4725_DIPPER) += board-dipper.o
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obj-$(CONFIG_JZ4720_VIRGO) += board-virgo.o
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+obj-$(CONFIG_JZ4740_QI_LB60) += board-qi_lb60.o
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# PM support
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diff -ruN linux-2.6.25.20.owrt.qi/arch/mips/Kconfig linux-2.6.25.20.owrt.qi.mod/arch/mips/Kconfig
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--- linux-2.6.25.20.owrt.qi/arch/mips/Kconfig 2009-08-05 03:02:12.000000000 +0200
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+++ linux-2.6.25.20.owrt.qi.mod/arch/mips/Kconfig 2009-08-06 18:56:17.000000000 +0200
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@@ -18,6 +18,14 @@
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prompt "System type"
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default SGI_IP22
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+config JZ4740_QI_LB60
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+ bool "Ingenic JZ4740 QI_LB60 board"
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+ select DMA_NONCOHERENT
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+ select SYS_HAS_CPU_MIPS32_R1
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+ select SYS_SUPPORTS_32BIT_KERNEL
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+ select SYS_SUPPORTS_LITTLE_ENDIAN
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+ select SOC_JZ4740
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+
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config JZ4730_PMP
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bool "Ingenic JZ4730 PMP board"
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select DMA_NONCOHERENT
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diff -ruN linux-2.6.25.20.owrt.qi/drivers/mtd/nand/jz4740_nand.c linux-2.6.25.20.owrt.qi.mod/drivers/mtd/nand/jz4740_nand.c
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--- linux-2.6.25.20.owrt.qi/drivers/mtd/nand/jz4740_nand.c 2009-08-05 03:02:12.000000000 +0200
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+++ linux-2.6.25.20.owrt.qi.mod/drivers/mtd/nand/jz4740_nand.c 2009-08-06 19:06:45.000000000 +0200
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@@ -278,6 +278,53 @@
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20, /* reserved blocks of mtd4 */
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20}; /* reserved blocks of mtd5 */
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#endif /* CONFIG_JZ4720_VIRGO */
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+
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+#ifdef CONFIG_JZ4740_QI_LB60
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+static struct mtd_partition partition_info[] = {
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+ { name: "NAND BOOT partition",
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+ offset: 0 * 0x100000,
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+ size: 4 * 0x100000,
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+ use_planes: 0 },
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+ { name: "NAND KERNEL partition",
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+ offset: 4 * 0x100000,
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+ size: 4 * 0x100000,
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+ use_planes: 0 },
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+ { name: "NAND ROOTFS partition",
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+ offset: 8 * 0x100000,
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+ size: 504 * 0x100000,
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+ use_planes: 0 },
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+ { name: "NAND DATA1 partition",
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+ offset: 512 * 0x100000,
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+ size: 512 * 0x100000,
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+ use_planes: 1 },
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+ { name: "NAND DATA2 partition",
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+ offset: 1024 * 0x100000,
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+ size: 512 * 0x100000,
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+ use_planes: 1 },
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+ { name: "NAND VFAT partition",
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+ offset: (1024 + 512) * 0x100000,
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+ size: 512 * 0x100000,
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+ use_planes: 1 },
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+};
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+
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+/* Define max reserved bad blocks for each partition.
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+ * This is used by the mtdblock-jz.c NAND FTL driver only.
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+ *
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+ * The NAND FTL driver reserves some good blocks which can't be
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+ * seen by the upper layer. When the bad block number of a partition
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+ * exceeds the max reserved blocks, then there is no more reserved
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+ * good blocks to be used by the NAND FTL driver when another bad
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+ * block generated.
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+ */
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+static int partition_reserved_badblocks[] = {
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+ 2, /* reserved blocks of mtd0 */
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+ 2, /* reserved blocks of mtd1 */
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+ 10, /* reserved blocks of mtd2 */
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+ 10, /* reserved blocks of mtd3 */
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+ 10, /* reserved blocks of mtd4 */
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+ 20}; /* reserved blocks of mtd5 */
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+#endif /* CONFIG_JZ4740_QI_LB60 */
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+
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/*-------------------------------------------------------------------------
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* Following three functions are exported and used by the mtdblock-jz.c
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* NAND FTL driver only.
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diff -ruN linux-2.6.25.20.owrt.qi/drivers/video/jzlcd.c linux-2.6.25.20.owrt.qi.mod/drivers/video/jzlcd.c
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--- linux-2.6.25.20.owrt.qi/drivers/video/jzlcd.c 2009-08-05 03:02:12.000000000 +0200
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+++ linux-2.6.25.20.owrt.qi.mod/drivers/video/jzlcd.c 2009-08-06 22:23:39.000000000 +0200
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@@ -126,15 +126,18 @@
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MODE_TFT_GEN | HSYNC_N | VSYNC_N | PCLK_N | DE_N,
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320, 240, 16, 60, 3, 3, 3, 3, 3, 85 /* 320x240 */
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#endif
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-#if defined(CONFIG_JZLCD_FOXCONN_PT035TN01) && defined(CONFIG_JZ4740_PAVO)
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- MODE_TFT_GEN | HSYNC_N | VSYNC_N | MODE_TFT_18BIT | PCLK_N,
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-// 320, 240, 18, 110, 1, 1, 10, 50, 10, 13
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- 320, 240, 18, 80, 1, 1, 10, 50, 10, 13
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-#endif
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-#if defined(CONFIG_JZLCD_FOXCONN_PT035TN01) && !(defined(CONFIG_JZ4740_PAVO))
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- MODE_TFT_GEN | HSYNC_N | VSYNC_N | PCLK_N,
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- 320, 240, 16, 110, 1, 1, 10, 50, 10, 13
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-#endif
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+#if defined(CONFIG_JZLCD_FOXCONN_PT035TN01)
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+ #if defined(CONFIG_JZ4740_PAVO)
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+ MODE_TFT_GEN | HSYNC_N | VSYNC_N | MODE_TFT_18BIT | PCLK_N,
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+ 320, 240, 18, 80, 1, 1, 10, 50, 10, 13
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+ #elif defined(CONFIG_JZ4740_QI_LB60)
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+ MODE_8BIT_SERIAL_TFT | PCLK_N | HSYNC_N | VSYNC_N,
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+ 320, 240, 32, 70, 1, 1, 273, 140, 1, 20
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+ #else
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+ MODE_TFT_GEN | HSYNC_N | VSYNC_N | PCLK_N,
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+ 320, 240, 16, 110, 1, 1, 10, 50, 10, 13
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+ #endif
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+#endif /* CONFIG_JZLCD_FOXCONN_PT035TN01 */
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#if defined(CONFIG_JZLCD_INNOLUX_PT035TN01_SERIAL)
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MODE_8BIT_SERIAL_TFT | PCLK_N | HSYNC_N | VSYNC_N,
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320, 240, 32, 60, 1, 1, 10, 50, 10, 13
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@@ -1523,7 +1526,7 @@
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cfb->pm->data = cfb;
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#endif
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- __lcd_display_on();
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+ __lcd_display_off();
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return 0;
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diff -ruN linux-2.6.25.20.owrt.qi/drivers/video/jzlcd.h linux-2.6.25.20.owrt.qi.mod/drivers/video/jzlcd.h
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--- linux-2.6.25.20.owrt.qi/drivers/video/jzlcd.h 2009-08-05 03:02:12.000000000 +0200
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+++ linux-2.6.25.20.owrt.qi.mod/drivers/video/jzlcd.h 2009-08-06 22:29:03.000000000 +0200
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@@ -363,7 +363,11 @@
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#if defined(CONFIG_JZLCD_FOXCONN_PT035TN01) || defined(CONFIG_JZLCD_INNOLUX_PT035TN01_SERIAL)
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#if defined(CONFIG_JZLCD_FOXCONN_PT035TN01) /* board pmp */
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-#define MODE 0xcd /* 24bit parellel RGB */
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+ #if defined(CONFIG_JZ4740_QI_LB60)
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+ #define MODE 0xc9
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+ #else
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+ #define MODE 0xcd /* 24bit parellel RGB */
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+ #endif
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#endif
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#if defined(CONFIG_JZLCD_INNOLUX_PT035TN01_SERIAL)
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#define MODE 0xc9 /* 8bit serial RGB */
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@@ -384,6 +388,11 @@
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#define SPCK (32*1+17) //LCD_CLS
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#define SPDA (32*2+12) //LCD_D12
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#define LCD_RET (32*2+23) //LCD_REV, GPC23
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+#elif defined(CONFIG_JZ4740_QI_LB60)
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+ #define SPEN (32*2+21) //LCD_SPL
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+ #define SPCK (32*2+23) //LCD_CLS
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+ #define SPDA (32*2+22) //LCD_D12
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+ #define LCD_RET (32*3+27)
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#if 0 /*old driver*/
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#define SPEN (32*1+18) //LCD_SPL
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#define SPCK (32*1+17) //LCD_CLS
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@@ -655,7 +663,7 @@
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/*#if defined(CONFIG_JZ4740_LEO) || defined(CONFIG_JZ4740_PAVO)*/
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#if defined(CONFIG_SOC_JZ4740)
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-#if defined(CONFIG_JZ4740_PAVO) || defined(CONFIG_JZ4740_LYRA)
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+#if defined(CONFIG_JZ4740_PAVO) || defined(CONFIG_JZ4740_LYRA) || defined(CONFIG_JZ4740_QI_LB60)
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#define GPIO_PWM 123 /* GP_D27 */
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#define PWM_CHN 4 /* pwm channel */
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#define PWM_FULL 101
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@@ -725,7 +733,7 @@
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do { \
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__gpio_set_pin(GPIO_DISP_OFF_N); \
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__lcd_special_on(); \
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- __lcd_set_backlight_level(80); \
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+ __lcd_set_backlight_level(20); \
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} while (0)
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#define __lcd_display_off() \
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diff -ruN linux-2.6.25.20.owrt.qi/include/asm-mips/mach-jz4740/board-qi_lb60.h linux-2.6.25.20.owrt.qi.mod/include/asm-mips/mach-jz4740/board-qi_lb60.h
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--- linux-2.6.25.20.owrt.qi/include/asm-mips/mach-jz4740/board-qi_lb60.h 1970-01-01 01:00:00.000000000 +0100
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+++ linux-2.6.25.20.owrt.qi.mod/include/asm-mips/mach-jz4740/board-qi_lb60.h 2009-08-06 22:11:42.000000000 +0200
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@@ -0,0 +1,79 @@
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+/*
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+ * linux/include/asm-mips/mach-jz4740/board-qi_lb60.h
|
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+ *
|
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+ * Copyright (c) 2009 Qi Hardware inc.,
|
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+ * Author: Xiangfu Liu <xiangfu@qi-hardware.com>
|
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+ *
|
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+ * This program is free software; you can redistribute it and/or modify
|
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+ * it under the terms of the GNU General Public License version 3 as
|
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+ * published by the Free Software Foundation.
|
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+ */
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+
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+#ifndef __ASM_JZ4740_QI_LB60_H__
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+#define __ASM_JZ4740_QI_LB60_H__
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+
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+/*
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+ * Frequencies of on-board oscillators
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+ */
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+#define JZ_EXTAL 12000000 /* Main extal freq: 12 MHz */
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+#define JZ_EXTAL2 32768 /* RTC extal freq: 32.768 KHz */
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+
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+/*
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+ * GPIO
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+ */
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+#define GPIO_DC_DETE_N (2 * 32 + 26)
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+#define GPIO_CHARG_STAT_N (2 * 32 + 27)
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+#define GPIO_LED_EN (2 * 32 + 28)
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+#define GPIO_LCD_CS (2 * 32 + 21)
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+#define GPIO_DISP_OFF_N (3 * 32 + 21)
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+#define GPIO_PWM (3 * 32 + 27)
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+
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+#define GPIO_AMP_EN (3 * 32 + 4)
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+
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+#define GPIO_SD_CD_N (3 * 32 + 0)
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+#define GPIO_SD_VCC_EN_N (3 * 32 + 2)
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+#define GPIO_SD_WP (3 * 32 + 16)
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+
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+#define GPIO_USB_DETE (3 * 32 + 28)
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+#define GPIO_BUZZ_PWM (3 * 32 + 27)
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+#define GPIO_UDC_HOTPLUG GPIO_USB_DETE
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+
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+#define GPIO_AUDIO_POP (1 * 32 + 29)
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+#define GPIO_COB_TEST (1 * 32 + 30)
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+
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+#define GPIO_KEYOUT_BASE (2 * 32 + 10)
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+#define GPIO_KEYIN_BASE (3 * 32 + 18)
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+#define GPIO_KEYIN_8 (3 * 32 + 26)
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+
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+/*
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+ * MMC/SD
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+ */
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+#define MSC_WP_PIN GPIO_SD_WP
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+#define MSC_HOTPLUG_PIN GPIO_SD_CD_N
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+#define MSC_HOTPLUG_IRQ (IRQ_GPIO_0 + GPIO_SD_CD_N)
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+
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+#define __msc_init_io() \
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+do { \
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+ __gpio_as_output(GPIO_SD_VCC_EN_N); \
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+ __gpio_as_input(GPIO_SD_CD_N); \
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+} while (0)
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+
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+#define __msc_enable_power() \
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+do { \
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+ __gpio_clear_pin(GPIO_SD_VCC_EN_N); \
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+} while (0)
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+
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+#define __msc_disable_power() \
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+do { \
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+ __gpio_set_pin(GPIO_SD_VCC_EN_N); \
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+} while (0)
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+
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+#define __msc_card_detected(s) \
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+({ \
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+ int detected = 1; \
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+ if (!__gpio_get_pin(GPIO_SD_CD_N)) \
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+ detected = 0; \
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+ detected; \
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+})
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+
|
||||
+#endif /* __ASM_JZ4740_QI_LB60_H__ */
|
||||
diff -ruN linux-2.6.25.20.owrt.qi/include/asm-mips/mach-jz4740/jz4740.h linux-2.6.25.20.owrt.qi.mod/include/asm-mips/mach-jz4740/jz4740.h
|
||||
--- linux-2.6.25.20.owrt.qi/include/asm-mips/mach-jz4740/jz4740.h 2009-08-05 03:02:12.000000000 +0200
|
||||
+++ linux-2.6.25.20.owrt.qi.mod/include/asm-mips/mach-jz4740/jz4740.h 2009-08-06 19:00:15.000000000 +0200
|
||||
@@ -43,6 +43,10 @@
|
||||
#include <asm/mach-jz4740/board-virgo.h>
|
||||
#endif
|
||||
|
||||
+#ifdef CONFIG_JZ4740_QI_LB60
|
||||
+#include <asm/mach-jz4740/board-qi_lb60.h>
|
||||
+#endif
|
||||
+
|
||||
/* Add other platform definition here ... */
|
||||
|
||||
|
||||
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Reference in New Issue
Block a user