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[adm5120] cleanup memory detection code, fix #2244
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@8705 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@ -25,12 +25,13 @@
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <asm/io.h>
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#include <asm/bootinfo.h>
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#include <asm/addrspace.h>
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#include <asm/mach-adm5120/adm5120_info.h>
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#include <asm/mach-adm5120/adm5120_defs.h>
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#include <asm/mach-adm5120/adm5120_switch.h>
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#include <adm5120_info.h>
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#include <adm5120_defs.h>
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#include <adm5120_switch.h>
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unsigned int adm5120_product_code;
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unsigned int adm5120_revision;
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@ -38,9 +39,6 @@ unsigned int adm5120_package;
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unsigned int adm5120_nand_boot;
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unsigned long adm5120_speed;
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#define SWITCH_READ(r) *(u32 *)(KSEG1ADDR(ADM5120_SWITCH_BASE)+(r))
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#define SWITCH_WRITE(r,v) *(u32 *)(KSEG1ADDR(ADM5120_SWITCH_BASE)+(r))=(v)
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/*
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* CPU settings detection
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*/
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@ -54,21 +52,21 @@ void adm5120_ndelay(u32 ns)
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{
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u32 t;
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SWITCH_WRITE(SWITCH_REG_TIMER, TIMER_PERIOD_DEFAULT);
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SWITCH_WRITE(SWITCH_REG_TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM));
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SW_WRITE_REG(TIMER, TIMER_PERIOD_DEFAULT);
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SW_WRITE_REG(TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM));
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t = (ns+640) / 640;
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t &= TIMER_PERIOD_MASK;
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SWITCH_WRITE(SWITCH_REG_TIMER, t | TIMER_TE);
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SW_WRITE_REG(TIMER, t | TIMER_TE);
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/* wait until the timer expires */
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do {
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t = SWITCH_READ(SWITCH_REG_TIMER_INT);
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t = SW_READ_REG(TIMER_INT);
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} while ((t & TIMER_INT_TOS) == 0);
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/* leave the timer disabled */
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SWITCH_WRITE(SWITCH_REG_TIMER, TIMER_PERIOD_DEFAULT);
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SWITCH_WRITE(SWITCH_REG_TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM));
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SW_WRITE_REG(TIMER, TIMER_PERIOD_DEFAULT);
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SW_WRITE_REG(TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM));
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}
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void __init adm5120_soc_init(void)
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@ -76,7 +74,7 @@ void __init adm5120_soc_init(void)
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u32 code;
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u32 clks;
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code = SWITCH_READ(SWITCH_REG_CODE);
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code = SW_READ_REG(CODE);
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adm5120_product_code = CODE_GET_PC(code);
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adm5120_revision = CODE_GET_REV(code);
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@ -25,19 +25,14 @@
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <asm/io.h>
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#include <asm/bootinfo.h>
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#include <asm/addrspace.h>
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#include <asm/mach-adm5120/adm5120_info.h>
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#include <asm/mach-adm5120/adm5120_defs.h>
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#include <asm/mach-adm5120/adm5120_switch.h>
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#include <asm/mach-adm5120/adm5120_mpmc.h>
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#define SWITCH_READ(r) *(u32 *)(KSEG1ADDR(ADM5120_SWITCH_BASE)+(r))
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#define SWITCH_WRITE(r,v) *(u32 *)(KSEG1ADDR(ADM5120_SWITCH_BASE)+(r))=(v)
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#define MPMC_READ(r) *(u32 *)(KSEG1ADDR(ADM5120_SWITCH_BASE)+(r))
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#define MPMC_WRITE(r,v) *(u32 *)(KSEG1ADDR(ADM5120_SWITCH_BASE)+(r))=(v)
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#include <adm5120_info.h>
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#include <adm5120_defs.h>
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#include <adm5120_switch.h>
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#include <adm5120_mpmc.h>
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#if 1
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# define mem_dbg(f, a...) printk("mem_detect: " f, ## a)
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@ -45,19 +40,19 @@
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# define mem_dbg(f, a...)
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#endif
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#define MEM_WR_DELAY 10000 /* 0.01 usec */
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unsigned long adm5120_memsize;
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#define MEM_READL(a) __raw_readl((void __iomem *)(a))
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#define MEM_WRITEL(a, v) __raw_writel((v), (void __iomem *)(a))
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static int __init mem_check_pattern(u8 *addr, unsigned long offs)
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{
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volatile u32 *p1 = (volatile u32 *)addr;
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volatile u32 *p2 = (volatile u32 *)(addr+offs);
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u32 *p1 = (u32 *)addr;
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u32 *p2 = (u32 *)(addr+offs);
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u32 t,u,v;
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/* save original value */
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t = *p1;
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u = *p2;
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t = MEM_READL(p1);
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u = MEM_READL(p2);
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if (t != u)
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return 0;
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@ -68,15 +63,17 @@ static int __init mem_check_pattern(u8 *addr, unsigned long offs)
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mem_dbg("write 0x%08X to 0x%08lX\n", v, (unsigned long)p1);
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*p1 = v;
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mem_dbg("delay %d ns\n", MEM_WR_DELAY);
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adm5120_ndelay(MEM_WR_DELAY);
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u = *p2;
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MEM_WRITEL(p1, v);
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/* flush write buffers */
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MPMC_WRITE_REG(CTRL, MPMC_READ_REG(CTRL) | MPMC_CTRL_DWB);
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u = MEM_READL(p2);
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mem_dbg("pattern at 0x%08lX is 0x%08X\n", (unsigned long)p2, u);
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/* restore original value */
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*p1 = t;
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MEM_WRITEL(p1, t);
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return (v == u);
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}
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@ -87,7 +84,7 @@ static void __init adm5120_detect_memsize(void)
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u32 size, maxsize;
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u8 *p;
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memctrl = SWITCH_READ(SWITCH_REG_MEMCTRL);
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memctrl = SW_READ_REG(MEMCTRL);
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switch (memctrl & MEMCTRL_SDRS_MASK) {
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case MEMCTRL_SDRS_4M:
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maxsize = 4 << 20;
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@ -103,11 +100,6 @@ static void __init adm5120_detect_memsize(void)
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break;
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}
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/* disable buffers for both SDRAM banks */
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mem_dbg("disable buffers for both banks\n");
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MPMC_WRITE(MPMC_REG_DC0, MPMC_READ(MPMC_REG_DC0) & ~DC_BE);
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MPMC_WRITE(MPMC_REG_DC1, MPMC_READ(MPMC_REG_DC1) & ~DC_BE);
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mem_dbg("checking for %uMB chip in 1st bank\n", maxsize >> 20);
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/* detect size of the 1st SDRAM bank */
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@ -159,15 +151,10 @@ static void __init adm5120_detect_memsize(void)
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memctrl |= MEMCTRL_SDRS_64M;
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break;
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}
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SWITCH_WRITE(SWITCH_REG_MEMCTRL, memctrl);
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SW_WRITE_REG(MEMCTRL, memctrl);
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}
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out:
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/* reenable buffer for both SDRAM banks */
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mem_dbg("enable buffers for both banks\n");
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MPMC_WRITE(MPMC_REG_DC0, MPMC_READ(MPMC_REG_DC0) | DC_BE);
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MPMC_WRITE(MPMC_REG_DC1, MPMC_READ(MPMC_REG_DC1) | DC_BE);
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mem_dbg("%dx%uMB memory found\n", (adm5120_memsize == size) ? 1 : 2 ,
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size >>20);
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}
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