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Code

[adm5120] cleanup memory detection code, fix #2244

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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@8705 3c298f89-4303-0410-b956-a3cf2f4a3e73
This commit is contained in:
juhosg 2007-09-09 12:50:32 +00:00
parent f9d0242a80
commit aa10218a50
2 changed files with 32 additions and 47 deletions
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24
target/linux/adm5120/files/arch/mips/adm5120/adm5120_info.c
View File

@ -25,12 +25,13 @@
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/init.h> #include <linux/init.h>
#include <asm/io.h>
#include <asm/bootinfo.h> #include <asm/bootinfo.h>
#include <asm/addrspace.h> #include <asm/addrspace.h>
#include <asm/mach-adm5120/adm5120_info.h> #include <adm5120_info.h>
#include <asm/mach-adm5120/adm5120_defs.h> #include <adm5120_defs.h>
#include <asm/mach-adm5120/adm5120_switch.h> #include <adm5120_switch.h>
unsigned int adm5120_product_code; unsigned int adm5120_product_code;
unsigned int adm5120_revision; unsigned int adm5120_revision;
@ -38,9 +39,6 @@ unsigned int adm5120_package;
unsigned int adm5120_nand_boot; unsigned int adm5120_nand_boot;
unsigned long adm5120_speed; unsigned long adm5120_speed;
#define SWITCH_READ(r) *(u32 *)(KSEG1ADDR(ADM5120_SWITCH_BASE)+(r))
#define SWITCH_WRITE(r,v) *(u32 *)(KSEG1ADDR(ADM5120_SWITCH_BASE)+(r))=(v)
/* /*
* CPU settings detection * CPU settings detection
*/ */
@ -54,21 +52,21 @@ void adm5120_ndelay(u32 ns)
{ {
u32 t; u32 t;
SWITCH_WRITE(SWITCH_REG_TIMER, TIMER_PERIOD_DEFAULT); SW_WRITE_REG(TIMER, TIMER_PERIOD_DEFAULT);
SWITCH_WRITE(SWITCH_REG_TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM)); SW_WRITE_REG(TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM));
t = (ns+640) / 640; t = (ns+640) / 640;
t &= TIMER_PERIOD_MASK; t &= TIMER_PERIOD_MASK;
SWITCH_WRITE(SWITCH_REG_TIMER, t | TIMER_TE); SW_WRITE_REG(TIMER, t | TIMER_TE);
/* wait until the timer expires */ /* wait until the timer expires */
do { do {
t = SWITCH_READ(SWITCH_REG_TIMER_INT); t = SW_READ_REG(TIMER_INT);
} while ((t & TIMER_INT_TOS) == 0); } while ((t & TIMER_INT_TOS) == 0);
/* leave the timer disabled */ /* leave the timer disabled */
SWITCH_WRITE(SWITCH_REG_TIMER, TIMER_PERIOD_DEFAULT); SW_WRITE_REG(TIMER, TIMER_PERIOD_DEFAULT);
SWITCH_WRITE(SWITCH_REG_TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM)); SW_WRITE_REG(TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM));
} }
void __init adm5120_soc_init(void) void __init adm5120_soc_init(void)
@ -76,7 +74,7 @@ void __init adm5120_soc_init(void)
u32 code; u32 code;
u32 clks; u32 clks;
code = SWITCH_READ(SWITCH_REG_CODE); code = SW_READ_REG(CODE);
adm5120_product_code = CODE_GET_PC(code); adm5120_product_code = CODE_GET_PC(code);
adm5120_revision = CODE_GET_REV(code); adm5120_revision = CODE_GET_REV(code);

55
target/linux/adm5120/files/arch/mips/adm5120/memory.c
View File

@ -25,19 +25,14 @@
#include <linux/types.h> #include <linux/types.h>
#include <linux/kernel.h> #include <linux/kernel.h>
#include <asm/io.h>
#include <asm/bootinfo.h> #include <asm/bootinfo.h>
#include <asm/addrspace.h> #include <asm/addrspace.h>
#include <asm/mach-adm5120/adm5120_info.h> #include <adm5120_info.h>
#include <asm/mach-adm5120/adm5120_defs.h> #include <adm5120_defs.h>
#include <asm/mach-adm5120/adm5120_switch.h> #include <adm5120_switch.h>
#include <asm/mach-adm5120/adm5120_mpmc.h> #include <adm5120_mpmc.h>
#define SWITCH_READ(r) *(u32 *)(KSEG1ADDR(ADM5120_SWITCH_BASE)+(r))
#define SWITCH_WRITE(r,v) *(u32 *)(KSEG1ADDR(ADM5120_SWITCH_BASE)+(r))=(v)
#define MPMC_READ(r) *(u32 *)(KSEG1ADDR(ADM5120_SWITCH_BASE)+(r))
#define MPMC_WRITE(r,v) *(u32 *)(KSEG1ADDR(ADM5120_SWITCH_BASE)+(r))=(v)
#if 1 #if 1
# define mem_dbg(f, a...) printk("mem_detect: " f, ## a) # define mem_dbg(f, a...) printk("mem_detect: " f, ## a)
@ -45,19 +40,19 @@
# define mem_dbg(f, a...) # define mem_dbg(f, a...)
#endif #endif
#define MEM_WR_DELAY 10000 /* 0.01 usec */
unsigned long adm5120_memsize; unsigned long adm5120_memsize;
#define MEM_READL(a) __raw_readl((void __iomem *)(a))
#define MEM_WRITEL(a, v) __raw_writel((v), (void __iomem *)(a))
static int __init mem_check_pattern(u8 *addr, unsigned long offs) static int __init mem_check_pattern(u8 *addr, unsigned long offs)
{ {
volatile u32 *p1 = (volatile u32 *)addr; u32 *p1 = (u32 *)addr;
volatile u32 *p2 = (volatile u32 *)(addr+offs); u32 *p2 = (u32 *)(addr+offs);
u32 t,u,v; u32 t,u,v;
/* save original value */ /* save original value */
t = *p1; t = MEM_READL(p1);
u = *p2; u = MEM_READL(p2);
if (t != u) if (t != u)
return 0; return 0;
@ -68,15 +63,17 @@ static int __init mem_check_pattern(u8 *addr, unsigned long offs)
mem_dbg("write 0x%08X to 0x%08lX\n", v, (unsigned long)p1); mem_dbg("write 0x%08X to 0x%08lX\n", v, (unsigned long)p1);
*p1 = v; MEM_WRITEL(p1, v);
mem_dbg("delay %d ns\n", MEM_WR_DELAY);
adm5120_ndelay(MEM_WR_DELAY); /* flush write buffers */
u = *p2; MPMC_WRITE_REG(CTRL, MPMC_READ_REG(CTRL) | MPMC_CTRL_DWB);
u = MEM_READL(p2);
mem_dbg("pattern at 0x%08lX is 0x%08X\n", (unsigned long)p2, u); mem_dbg("pattern at 0x%08lX is 0x%08X\n", (unsigned long)p2, u);
/* restore original value */ /* restore original value */
*p1 = t; MEM_WRITEL(p1, t);
return (v == u); return (v == u);
} }
@ -87,7 +84,7 @@ static void __init adm5120_detect_memsize(void)
u32 size, maxsize; u32 size, maxsize;
u8 *p; u8 *p;
memctrl = SWITCH_READ(SWITCH_REG_MEMCTRL); memctrl = SW_READ_REG(MEMCTRL);
switch (memctrl & MEMCTRL_SDRS_MASK) { switch (memctrl & MEMCTRL_SDRS_MASK) {
case MEMCTRL_SDRS_4M: case MEMCTRL_SDRS_4M:
maxsize = 4 << 20; maxsize = 4 << 20;
@ -103,11 +100,6 @@ static void __init adm5120_detect_memsize(void)
break; break;
} }
/* disable buffers for both SDRAM banks */
mem_dbg("disable buffers for both banks\n");
MPMC_WRITE(MPMC_REG_DC0, MPMC_READ(MPMC_REG_DC0) & ~DC_BE);
MPMC_WRITE(MPMC_REG_DC1, MPMC_READ(MPMC_REG_DC1) & ~DC_BE);
mem_dbg("checking for %uMB chip in 1st bank\n", maxsize >> 20); mem_dbg("checking for %uMB chip in 1st bank\n", maxsize >> 20);
/* detect size of the 1st SDRAM bank */ /* detect size of the 1st SDRAM bank */
@ -159,15 +151,10 @@ static void __init adm5120_detect_memsize(void)
memctrl |= MEMCTRL_SDRS_64M; memctrl |= MEMCTRL_SDRS_64M;
break; break;
} }
SWITCH_WRITE(SWITCH_REG_MEMCTRL, memctrl); SW_WRITE_REG(MEMCTRL, memctrl);
} }
out: out:
/* reenable buffer for both SDRAM banks */
mem_dbg("enable buffers for both banks\n");
MPMC_WRITE(MPMC_REG_DC0, MPMC_READ(MPMC_REG_DC0) | DC_BE);
MPMC_WRITE(MPMC_REG_DC1, MPMC_READ(MPMC_REG_DC1) | DC_BE);
mem_dbg("%dx%uMB memory found\n", (adm5120_memsize == size) ? 1 : 2 , mem_dbg("%dx%uMB memory found\n", (adm5120_memsize == size) ? 1 : 2 ,
size >>20); size >>20);
} }