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git://projects.qi-hardware.com/openwrt-xburst.git
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[ramips] add ethernet support for rt5350
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33548 3c298f89-4303-0410-b956-a3cf2f4a3e73
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@ -54,6 +54,9 @@
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#define RAMIPS_TX_DLY_INT BIT(1)
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#define RAMIPS_RX_DLY_INT BIT(0)
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#define RT5350_RX_DLY_INT BIT(30)
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#define RT5350_TX_DLY_INT BIT(28)
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/* registers */
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#define RAMIPS_FE_OFFSET 0x0000
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#define RAMIPS_GDMA_OFFSET 0x0020
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@ -65,6 +68,9 @@
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#define RAMIPS_CMTABLE_OFFSET 0x0400
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#define RAMIPS_POLICYTABLE_OFFSET 0x1000
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#define RT5350_PDMA_OFFSET 0x0800
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#define RT5350_SDM_OFFSET 0x0c00
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#define RAMIPS_MDIO_ACCESS (RAMIPS_FE_OFFSET + 0x00)
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#define RAMIPS_MDIO_CFG (RAMIPS_FE_OFFSET + 0x04)
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#define RAMIPS_FE_GLO_CFG (RAMIPS_FE_OFFSET + 0x08)
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@ -94,6 +100,38 @@
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#define RAMIPS_CDMA_CSG_CFG (RAMIPS_CDMA_OFFSET + 0x00)
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#define RAMIPS_CDMA_SCH_CFG (RAMIPS_CDMA_OFFSET + 0x04)
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#define RT5350_TX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x00)
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#define RT5350_TX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x04)
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#define RT5350_TX_CTX_IDX0 (RT5350_PDMA_OFFSET + 0x08)
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#define RT5350_TX_DTX_IDX0 (RT5350_PDMA_OFFSET + 0x0C)
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#define RT5350_TX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x10)
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#define RT5350_TX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x14)
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#define RT5350_TX_CTX_IDX1 (RT5350_PDMA_OFFSET + 0x18)
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#define RT5350_TX_DTX_IDX1 (RT5350_PDMA_OFFSET + 0x1C)
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#define RT5350_TX_BASE_PTR2 (RT5350_PDMA_OFFSET + 0x20)
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#define RT5350_TX_MAX_CNT2 (RT5350_PDMA_OFFSET + 0x24)
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#define RT5350_TX_CTX_IDX2 (RT5350_PDMA_OFFSET + 0x28)
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#define RT5350_TX_DTX_IDX2 (RT5350_PDMA_OFFSET + 0x2C)
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#define RT5350_TX_BASE_PTR3 (RT5350_PDMA_OFFSET + 0x30)
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#define RT5350_TX_MAX_CNT3 (RT5350_PDMA_OFFSET + 0x34)
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#define RT5350_TX_CTX_IDX3 (RT5350_PDMA_OFFSET + 0x38)
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#define RT5350_TX_DTX_IDX3 (RT5350_PDMA_OFFSET + 0x3C)
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#define RT5350_RX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x100)
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#define RT5350_RX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x104)
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#define RT5350_RX_CALC_IDX0 (RT5350_PDMA_OFFSET + 0x108)
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#define RT5350_RX_DRX_IDX0 (RT5350_PDMA_OFFSET + 0x10C)
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#define RT5350_RX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x110)
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#define RT5350_RX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x114)
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#define RT5350_RX_CALC_IDX1 (RT5350_PDMA_OFFSET + 0x118)
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#define RT5350_RX_DRX_IDX1 (RT5350_PDMA_OFFSET + 0x11C)
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#define RT5350_PDMA_GLO_CFG (RT5350_PDMA_OFFSET + 0x204)
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#define RT5350_PDMA_RST_CFG (RT5350_PDMA_OFFSET + 0x208)
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#define RT5350_DLY_INT_CFG (RT5350_PDMA_OFFSET + 0x20c)
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#define RT5350_FE_INT_STATUS (RT5350_PDMA_OFFSET + 0x220)
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#define RT5350_FE_INT_ENABLE (RT5350_PDMA_OFFSET + 0x228)
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#define RT5350_PDMA_SCH_CFG (RT5350_PDMA_OFFSET + 0x280)
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#define RAMIPS_PDMA_GLO_CFG (RAMIPS_PDMA_OFFSET + 0x00)
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#define RAMIPS_PDMA_RST_CFG (RAMIPS_PDMA_OFFSET + 0x04)
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#define RAMIPS_PDMA_SCH_CFG (RAMIPS_PDMA_OFFSET + 0x08)
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@ -123,6 +161,22 @@
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#define RAMIPS_RX_CALC_IDX1 (RAMIPS_PDMA_OFFSET + 0x68)
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#define RAMIPS_RX_DRX_IDX1 (RAMIPS_PDMA_OFFSET + 0x6C)
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#define RT5350_SDM_CFG (RT5350_SDM_OFFSET + 0x00) //Switch DMA configuration
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#define RT5350_SDM_RRING (RT5350_SDM_OFFSET + 0x04) //Switch DMA Rx Ring
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#define RT5350_SDM_TRING (RT5350_SDM_OFFSET + 0x08) //Switch DMA Tx Ring
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#define RT5350_SDM_MAC_ADRL (RT5350_SDM_OFFSET + 0x0C) //Switch MAC address LSB
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#define RT5350_SDM_MAC_ADRH (RT5350_SDM_OFFSET + 0x10) //Switch MAC Address MSB
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#define RT5350_SDM_TPCNT (RT5350_SDM_OFFSET + 0x100) //Switch DMA Tx packet count
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#define RT5350_SDM_TBCNT (RT5350_SDM_OFFSET + 0x104) //Switch DMA Tx byte count
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#define RT5350_SDM_RPCNT (RT5350_SDM_OFFSET + 0x108) //Switch DMA rx packet count
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#define RT5350_SDM_RBCNT (RT5350_SDM_OFFSET + 0x10C) //Switch DMA rx byte count
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#define RT5350_SDM_CS_ERR (RT5350_SDM_OFFSET + 0x110) //Switch DMA rx checksum error count
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#define RT5350_SDM_ICS_EN BIT(16)
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#define RT5350_SDM_TCS_EN BIT(17)
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#define RT5350_SDM_UCS_EN BIT(18)
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/* MDIO_CFG register bits */
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#define RAMIPS_MDIO_CFG_AUTO_POLL_EN BIT(29)
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#define RAMIPS_MDIO_CFG_GP1_BP_EN BIT(16)
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@ -33,10 +33,12 @@
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#define MAX_RX_LENGTH 1600
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#ifdef CONFIG_RALINK_RT305X
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#include <rt305x.h>
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#include "ramips_esw.c"
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#else
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static inline int rt305x_esw_init(void) { return 0; }
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static inline void rt305x_esw_exit(void) { }
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static inline int soc_is_rt5350(void) { return 0; }
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#endif
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#define phys_to_bus(a) (a & 0x1FFFFFFF)
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@ -47,6 +49,9 @@ static inline void rt305x_esw_exit(void) { }
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#define RADEBUG(fmt, args...) do {} while (0)
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#endif
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#define RX_DLY_INT ((soc_is_rt5350())?(RT5350_RX_DLY_INT):(RAMIPS_RX_DLY_INT))
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#define TX_DLY_INT ((soc_is_rt5350())?(RT5350_TX_DLY_INT):(RAMIPS_TX_DLY_INT))
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enum raeth_reg {
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RAETH_REG_PDMA_GLO_CFG = 0,
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RAETH_REG_PDMA_RST_CFG,
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@ -76,6 +81,20 @@ static const u32 ramips_reg_table[RAETH_REG_COUNT] = {
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[RAETH_REG_FE_INT_STATUS] = RAMIPS_FE_INT_STATUS,
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};
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static const u32 rt5350_reg_table[RAETH_REG_COUNT] = {
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[RAETH_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
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[RAETH_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
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[RAETH_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
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[RAETH_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
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[RAETH_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
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[RAETH_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
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[RAETH_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
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[RAETH_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
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[RAETH_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
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[RAETH_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
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[RAETH_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
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};
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static struct net_device * ramips_dev;
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static void __iomem *ramips_fe_base = 0;
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@ -83,7 +102,10 @@ static inline u32 get_reg_offset(enum raeth_reg reg)
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{
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const u32 *table;
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table = ramips_reg_table;
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if (soc_is_rt5350())
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table = rt5350_reg_table;
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else
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table = ramips_reg_table;
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return table[reg];
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}
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@ -133,9 +155,15 @@ ramips_fe_int_enable(u32 mask)
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static inline void
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ramips_hw_set_macaddr(unsigned char *mac)
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{
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ramips_fe_wr((mac[0] << 8) | mac[1], RAMIPS_GDMA1_MAC_ADRH);
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ramips_fe_wr((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
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RAMIPS_GDMA1_MAC_ADRL);
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if (soc_is_rt5350()) {
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ramips_fe_wr((mac[0] << 8) | mac[1], RT5350_SDM_MAC_ADRH);
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ramips_fe_wr((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
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RT5350_SDM_MAC_ADRL);
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} else {
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ramips_fe_wr((mac[0] << 8) | mac[1], RAMIPS_GDMA1_MAC_ADRH);
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ramips_fe_wr((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
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RAMIPS_GDMA1_MAC_ADRL);
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}
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}
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static struct sk_buff *
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@ -825,7 +853,7 @@ ramips_eth_rx_hw(unsigned long ptr)
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if (max_rx == 0)
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tasklet_schedule(&re->rx_tasklet);
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else
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ramips_fe_int_enable(RAMIPS_RX_DLY_INT);
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ramips_fe_int_enable(RX_DLY_INT);
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}
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static void
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@ -858,7 +886,7 @@ ramips_eth_tx_housekeeping(unsigned long ptr)
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netdev_completed_queue(dev, pkts_compl, bytes_compl);
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spin_unlock(&re->page_lock);
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ramips_fe_int_enable(RAMIPS_TX_DLY_INT);
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ramips_fe_int_enable(TX_DLY_INT);
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}
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static void
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@ -883,13 +911,13 @@ ramips_eth_irq(int irq, void *dev)
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ramips_fe_twr(status, RAETH_REG_FE_INT_STATUS);
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if (status & RAMIPS_RX_DLY_INT) {
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ramips_fe_int_disable(RAMIPS_RX_DLY_INT);
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if (status & RX_DLY_INT) {
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ramips_fe_int_disable(RX_DLY_INT);
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tasklet_schedule(&re->rx_tasklet);
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}
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if (status & RAMIPS_TX_DLY_INT) {
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ramips_fe_int_disable(RAMIPS_TX_DLY_INT);
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if (status & TX_DLY_INT) {
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ramips_fe_int_disable(TX_DLY_INT);
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tasklet_schedule(&re->tx_housekeeping_tasklet);
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}
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@ -933,14 +961,20 @@ ramips_eth_open(struct net_device *dev)
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ramips_phy_start(re);
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ramips_fe_twr(RAMIPS_DELAY_INIT, RAETH_REG_DLY_INT_CFG);
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ramips_fe_twr(RAMIPS_TX_DLY_INT | RAMIPS_RX_DLY_INT, RAETH_REG_FE_INT_ENABLE);
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ramips_fe_wr(ramips_fe_rr(RAMIPS_GDMA1_FWD_CFG) &
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~(RAMIPS_GDM1_ICS_EN | RAMIPS_GDM1_TCS_EN | RAMIPS_GDM1_UCS_EN | 0xffff),
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RAMIPS_GDMA1_FWD_CFG);
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ramips_fe_wr(ramips_fe_rr(RAMIPS_CDMA_CSG_CFG) &
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~(RAMIPS_ICS_GEN_EN | RAMIPS_TCS_GEN_EN | RAMIPS_UCS_GEN_EN),
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RAMIPS_CDMA_CSG_CFG);
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ramips_fe_wr(RAMIPS_PSE_FQFC_CFG_INIT, RAMIPS_PSE_FQ_CFG);
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ramips_fe_twr(TX_DLY_INT | RX_DLY_INT, RAETH_REG_FE_INT_ENABLE);
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if (soc_is_rt5350()) {
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ramips_fe_wr(ramips_fe_rr(RT5350_SDM_CFG) &
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~(RT5350_SDM_ICS_EN | RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN | 0xffff),
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RT5350_SDM_CFG);
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} else {
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ramips_fe_wr(ramips_fe_rr(RAMIPS_GDMA1_FWD_CFG) &
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~(RAMIPS_GDM1_ICS_EN | RAMIPS_GDM1_TCS_EN | RAMIPS_GDM1_UCS_EN | 0xffff),
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RAMIPS_GDMA1_FWD_CFG);
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ramips_fe_wr(ramips_fe_rr(RAMIPS_CDMA_CSG_CFG) &
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~(RAMIPS_ICS_GEN_EN | RAMIPS_TCS_GEN_EN | RAMIPS_UCS_GEN_EN),
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RAMIPS_CDMA_CSG_CFG);
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ramips_fe_wr(RAMIPS_PSE_FQFC_CFG_INIT, RAMIPS_PSE_FQ_CFG);
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}
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ramips_fe_wr(1, RAMIPS_FE_RST_GL);
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ramips_fe_wr(0, RAMIPS_FE_RST_GL);
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