sie-ceimtun/Examples/Beta1/logic/build/project_summary.xml

<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
     by the Xilinx ISE software.  Any direct editing or
     changes made to this file may result in unpredictable
     behavior or data corruption.  It is strongly advised that
     users do not edit the contents of this file. -->
<DesignSummary rev="20">
<CmdHistory>
</CmdHistory>
</DesignSummary>
Uploaded the first Beta to test in the development group 2010-10-31 02:34:22 +03:00			`<?xml version="1.0" encoding="UTF-8"?>`
			`<!-- IMPORTANT: This is an internal file that has been generated`
			`by the Xilinx ISE software. Any direct editing or`
			`changes made to this file may result in unpredictable`
			`behavior or data corruption. It is strongly advised that`
			`users do not edit the contents of this file. -->`
Added .bit with hbridge pins and with testing pins 2010-10-31 19:24:46 +02:00			`<DesignSummary rev="20">`
Uploaded the first Beta to test in the development group 2010-10-31 02:34:22 +03:00			`<CmdHistory>`
			`</CmdHistory>`
			`</DesignSummary>`