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Added .bit with hbridge pins and with testing pins

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This commit is contained in:
Erwin Lopez 2010-10-31 12:24:46 -05:00
parent cc225fc088
commit 551a96ecc3
29 changed files with 465 additions and 465 deletions
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Examples/Beta1/logic/beta.bit
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Examples/Beta1/logic/beta.ucf
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@ -5,22 +5,22 @@ NET reset LOC = "P30"; #WARNING change to another pin
#NET led2 LOC = "P71"; #Pin superior izquierdo
#NET OD2 LOC = "P66";
#NET OD3 LOC = "P63";
NET quadA LOC = "P67";
NET quadB LOC = "P68";
NET quadC LOC = "P70";
NET quadD LOC = "P71";
#NET quadA LOC = "P67";
#NET quadB LOC = "P68";
#NET quadC LOC = "P70";
#NET quadD LOC = "P71";
NET quadA LOC = "P36"; #PINES DE PRUEBA
NET quadB LOC = "P35"; #PINES DE PRUEBA
NET quadC LOC = "P34"; #PINES DE PRUEBA
NET quadD LOC = "P33"; #PINES DE PRUEBA
NET "hbridge<3>" LOC = "P53";
NET "hbridge<2>" LOC = "P54";
NET "hbridge<1>" LOC = "P49";
NET "hbridge<0>" LOC = "P48";
#NET "hbridge<3>" LOC = "P71";#PINES DE PRUEBA
#NET "hbridge<2>" LOC = "P70"; #PINES DE PRUEBA
#NET "hbridge<1>" LOC = "P68"; #PINES DE PRUEBA
#NET "hbridge<0>" LOC = "P66"; #PINES DE PRUEBA
#NET "hbridge<3>" LOC = "P53";
#NET "hbridge<2>" LOC = "P54";
#NET "hbridge<1>" LOC = "P49";
#NET "hbridge<0>" LOC = "P48";
NET "hbridge<3>" LOC = "P71";#PINES DE PRUEBA
NET "hbridge<2>" LOC = "P70"; #PINES DE PRUEBA
NET "hbridge<1>" LOC = "P68"; #PINES DE PRUEBA
NET "hbridge<0>" LOC = "P66"; #PINES DE PRUEBA
#ADDRESS BUS
NET "addr<12>" LOC = "P90";

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Examples/Beta1/logic/beta_pineshbridge.bit Normal file
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Examples/Beta1/logic/build/beta_map.xrpt
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@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Map" timeStamp="Sat Oct 30 21:33:32 2010">
<application stringID="Map" timeStamp="Sun Oct 31 12:20:39 2010">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@ -53,8 +53,8 @@
<item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/>
<item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/>
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="0"/>
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="375988"/>
<item stringID="MAP_TOTAL_REAL_TIME" value="2 secs "/>
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="375984"/>
<item stringID="MAP_TOTAL_REAL_TIME" value="4 secs "/>
<item stringID="MAP_TOTAL_CPU_TIME" value="2 secs "/>
</section>
<section stringID="MAP_SLICE_REPORTING">

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Examples/Beta1/logic/build/beta_par.xrpt
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@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="par" timeStamp="Sat Oct 30 21:33:35 2010">
<application stringID="par" timeStamp="Sun Oct 31 12:20:43 2010">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
@ -47,12 +47,12 @@
</task>
<task stringID="PAR_PAR">
<section stringID="PAR_DESIGN_SUMMARY">
<item stringID="PAR_REAL_TIME_COMPLETION_ROUTER" value="26 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_ROUTER" value="22 secs "/>
<item stringID="PAR_REAL_TIME_COMPLETION_ROUTER" value="23 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_ROUTER" value="21 secs "/>
<item dataType="int" stringID="PAR_UNROUTES" value="0"/>
<item dataType="float" stringID="PAR_TIMING_SCORE" value="0.000000"/>
<item stringID="PAR_REAL_TIME_COMPLETION_PAR" value="27 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_PAR" value="22 secs "/>
<item stringID="PAR_REAL_TIME_COMPLETION_PAR" value="24 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_PAR" value="21 secs "/>
</section>
</task>
<task stringID="PAR_par">

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Examples/Beta1/logic/build/project.bld
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@ -27,7 +27,7 @@ NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Total memory usage is 235692 kilobytes
Total memory usage is 235700 kilobytes
Writing NGD file "project.ngd" ...
Total REAL time to NGDBUILD completion: 3 sec

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Examples/Beta1/logic/build/project.map
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@ -8,7 +8,7 @@ Target Device : xc3s500e
Target Package : vq100
Target Speed : -4
Mapper Version : spartan3e -- $Revision: 1.52 $
Mapped Date : Sat Oct 30 21:33:29 2010
Mapped Date : Sun Oct 31 12:20:35 2010
Mapping design into LUTs...
Writing file project.ngm...
@ -47,7 +47,7 @@ Logic Distribution:
Average Fanout of Non-Clock Nets: 2.51
Peak Memory Usage: 367 MB
Total REAL time to MAP completion: 2 secs
Total REAL time to MAP completion: 4 secs
Total CPU time to MAP completion: 2 secs
NOTES:

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Examples/Beta1/logic/build/project.mrp
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@ -8,7 +8,7 @@ Target Device : xc3s500e
Target Package : vq100
Target Speed : -4
Mapper Version : spartan3e -- $Revision: 1.52 $
Mapped Date : Sat Oct 30 21:33:29 2010
Mapped Date : Sun Oct 31 12:20:35 2010
Design Summary
--------------
@ -37,7 +37,7 @@ Logic Distribution:
Average Fanout of Non-Clock Nets: 2.51
Peak Memory Usage: 367 MB
Total REAL time to MAP completion: 2 secs
Total REAL time to MAP completion: 4 secs
Total CPU time to MAP completion: 2 secs
NOTES:

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@ -1,5 +1,5 @@
//! **************************************************************************
// Written by: Map M.63c on Sat Oct 30 21:33:31 2010
// Written by: Map M.63c on Sun Oct 31 12:20:38 2010
//! **************************************************************************
SCHEMATIC START;

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Examples/Beta1/logic/build/project_ngdbuild.xrpt
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@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Sat Oct 30 21:33:27 2010">
<application stringID="NgdBuild" timeStamp="Sun Oct 31 12:20:33 2010">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>

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Examples/Beta1/logic/build/project_r.bgn
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@ -4,7 +4,7 @@ Loading device for application Rf_Device from file '3s500e.nph' in environment
/home/erwin/Xilinxs/12.2/ISE_DS/ISE/.
"beta" is an NCD, version 3.2, device xc3s500e, package vq100, speed -4
Sat Oct 30 21:34:07 2010
Sun Oct 31 12:21:10 2010
/home/erwin/Xilinxs/12.2/ISE_DS/ISE/bin/lin64/unwrapped/bitgen -l -w -g TdoPin:PULLNONE -g DonePin:PULLUP -g CRC:enable -g StartUpClk:CCLK project_r.ncd

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Examples/Beta1/logic/build/project_r.drc
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@ -1,7 +1,7 @@
Release 12.2 Drc M.63c (lin64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Sat Oct 30 21:34:07 2010
Sun Oct 31 12:21:10 2010
drc -z project_r.ncd

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Examples/Beta1/logic/build/project_r.ll
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@ -1,5 +1,5 @@
Revision 3
; Created by bitgen M.63c at Sat Oct 30 21:34:08 2010
; Created by bitgen M.63c at Sun Oct 31 12:21:12 2010
; Bit lines have the following form:
; <offset> <frame address> <frame offset> <information>
; <information> may be zero or more <kw>=<value> pairs

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Examples/Beta1/logic/build/project_r.pad
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@ -1,7 +1,7 @@
Release 12.2 - par M.63c (lin64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Sat Oct 30 21:34:01 2010
Sun Oct 31 12:21:06 2010
# NOTE: This file is designed to be imported into a spreadsheet program

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Examples/Beta1/logic/build/project_r.par
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@ -1,7 +1,7 @@
Release 12.2 par M.63c (lin64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
dellerwin:: Sat Oct 30 21:33:34 2010
dellerwin:: Sun Oct 31 12:20:42 2010
par -w project.ncd project_r.ncd
@ -62,7 +62,7 @@ Finished initial Timing Analysis. REAL time: 2 secs
Starting Placer
Total REAL time at the beginning of Placer: 2 secs
Total CPU time at the beginning of Placer: 2 secs
Total CPU time at the beginning of Placer: 1 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:cb32ae9e) REAL time: 3 secs
@ -75,13 +75,13 @@ Phase 3.31 Local Placement Optimization (Checksum:cb32ae9e) REAL time: 3 secs
Phase 4.2 Initial Clock and IO Placement
Phase 4.2 Initial Clock and IO Placement (Checksum:534cc618) REAL time: 3 secs
Phase 4.2 Initial Clock and IO Placement (Checksum:534cc618) REAL time: 4 secs
Phase 5.30 Global Clock Region Assignment
Phase 5.30 Global Clock Region Assignment (Checksum:534cc618) REAL time: 3 secs
Phase 5.30 Global Clock Region Assignment (Checksum:534cc618) REAL time: 4 secs
Phase 6.36 Local Placement Optimization
Phase 6.36 Local Placement Optimization (Checksum:534cc618) REAL time: 3 secs
Phase 6.36 Local Placement Optimization (Checksum:534cc618) REAL time: 4 secs
Phase 7.8 Global Placement
....
@ -89,19 +89,19 @@ Phase 7.8 Global Placement
...
...
....
Phase 7.8 Global Placement (Checksum:b10264e) REAL time: 12 secs
Phase 7.8 Global Placement (Checksum:b10264e) REAL time: 11 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:b10264e) REAL time: 12 secs
Phase 8.5 Local Placement Optimization (Checksum:b10264e) REAL time: 11 secs
Phase 9.18 Placement Optimization
Phase 9.18 Placement Optimization (Checksum:a0b1bc3c) REAL time: 13 secs
Phase 9.18 Placement Optimization (Checksum:a0b1bc3c) REAL time: 12 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:a0b1bc3c) REAL time: 13 secs
Phase 10.5 Local Placement Optimization (Checksum:a0b1bc3c) REAL time: 12 secs
Total REAL time to Placer completion: 13 secs
Total CPU time to Placer completion: 11 secs
Total REAL time to Placer completion: 12 secs
Total CPU time to Placer completion: 10 secs
Writing design to file project_r.ncd
@ -109,32 +109,32 @@ Writing design to file project_r.ncd
Starting Router
Phase 1 : 776 unrouted; REAL time: 19 secs
Phase 1 : 776 unrouted; REAL time: 17 secs
Phase 2 : 652 unrouted; REAL time: 19 secs
Phase 2 : 652 unrouted; REAL time: 17 secs
Phase 3 : 110 unrouted; REAL time: 19 secs
Phase 3 : 110 unrouted; REAL time: 17 secs
Phase 4 : 129 unrouted; (Par is working to improve performance) REAL time: 20 secs
Phase 4 : 129 unrouted; (Par is working to improve performance) REAL time: 18 secs
Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 20 secs
Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 18 secs
Updating file: project_r.ncd with current fully routed design.
Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 21 secs
Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 19 secs
Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 26 secs
Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 23 secs
Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 26 secs
Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 23 secs
Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 26 secs
Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 23 secs
Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 26 secs
Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 23 secs
Phase 11 : 0 unrouted; (Par is working to improve performance) REAL time: 26 secs
Phase 11 : 0 unrouted; (Par is working to improve performance) REAL time: 23 secs
Total REAL time to Router completion: 26 secs
Total CPU time to Router completion: 22 secs
Total REAL time to Router completion: 23 secs
Total CPU time to Router completion: 21 secs
Partition Implementation Status
-------------------------------
@ -186,8 +186,8 @@ Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 27 secs
Total CPU time to PAR completion: 22 secs
Total REAL time to PAR completion: 24 secs
Total CPU time to PAR completion: 21 secs
Peak Memory Usage: 366 MB

2
Examples/Beta1/logic/build/project_r.twr
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@ -128,7 +128,7 @@ noe |sram_data<7> | 9.240|
---------------+---------------+---------+
Analysis completed Sat Oct 30 21:34:04 2010
Analysis completed Sun Oct 31 12:21:08 2010
--------------------------------------------------------------------------------
Trace Settings:

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Examples/Beta1/logic/build/project_r.unroutes
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@ -1,7 +1,7 @@
Release 12.2 - par M.63c (lin64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Sat Oct 30 21:34:01 2010
Sun Oct 31 12:21:06 2010
All signals are completely routed.

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Examples/Beta1/logic/build/project_r_pad.csv
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@ -1,7 +1,7 @@
#Release 12.2 - par M.63c (lin64)
#Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
#Sat Oct 30 21:34:01 2010
#Sun Oct 31 12:21:06 2010
#
## NOTE: This file is designed to be imported into a spreadsheet program

1 #Release 12.2 - par M.63c (lin64)
2 #Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
3 #Sat Oct 30 21:34:01 2010 #Sun Oct 31 12:21:06 2010
4 #
5 ## NOTE: This file is designed to be imported into a spreadsheet program
6 # such as Microsoft Excel for viewing, printing and sorting. The |
7 # character is used as the data field separator. This file is also designed

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Examples/Beta1/logic/build/project_r_pad.txt
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@ -1,7 +1,7 @@
Release 12.2 - par M.63c (lin64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Sat Oct 30 21:34:01 2010
Sun Oct 31 12:21:06 2010
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:

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Examples/Beta1/logic/build/project_summary.xml
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@ -4,7 +4,7 @@
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DesignSummary rev="16">
<DesignSummary rev="20">
<CmdHistory>
</CmdHistory>
</DesignSummary>

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Examples/Beta1/logic/build/usage_statistics_webtalk.html
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@ -17,7 +17,7 @@
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project ID (random number)</B></TD>
<TD><xtag-property name="RandomID">c2aacd1c16a742efb7b16ebde1b15f3a</xtag-property>.<xtag-property name="ProjectID">3e658027d9514d018043b63a2e613df7</xtag-property>.<xtag-property name="ProjectIteration">8</xtag-property></TD>
<TD><xtag-property name="RandomID">c2aacd1c16a742efb7b16ebde1b15f3a</xtag-property>.<xtag-property name="ProjectID">3e658027d9514d018043b63a2e613df7</xtag-property>.<xtag-property name="ProjectIteration">10</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Target Package:</B></TD>
<TD><xtag-property name="TargetPackage">vq100</xtag-property></TD>
</TR>
@ -29,7 +29,7 @@
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Date Generated</B></TD>
<TD><xtag-property name="Date Generated">2010-10-30T21:34:13</xtag-property></TD>
<TD><xtag-property name="Date Generated">2010-10-31T12:21:16</xtag-property></TD>
<TD BGCOLOR='#FFFF99'><B>Tool Flow</B></TD>
<TD><xtag-property name="ToolFlow">CommandLine</xtag-property></TD>
</TR>
@ -696,8 +696,8 @@
&nbsp;<BR><TABLE BORDER CELLSPACING=0 WIDTH='100%'><xtag-section name="RunStatistics"><TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=8><B>Software Quality</B></TD></TR><TR ALIGN=LEFT><TD COLSPAN=8><B>Run Statistics</B></TD></TR>
<tr>
<td><xtag-program-name>bitgen</xtag-program-name></td>
<td><xtag-total-run-started>90</xtag-total-run-started></td>
<td><xtag-total-run-finished>90</xtag-total-run-finished></td>
<td><xtag-total-run-started>92</xtag-total-run-started></td>
<td><xtag-total-run-finished>92</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
@ -706,8 +706,8 @@
</tr>
<tr>
<td><xtag-program-name>map</xtag-program-name></td>
<td><xtag-total-run-started>110</xtag-total-run-started></td>
<td><xtag-total-run-finished>108</xtag-total-run-finished></td>
<td><xtag-total-run-started>113</xtag-total-run-started></td>
<td><xtag-total-run-finished>111</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
@ -716,8 +716,8 @@
</tr>
<tr>
<td><xtag-program-name>ngdbuild</xtag-program-name></td>
<td><xtag-total-run-started>114</xtag-total-run-started></td>
<td><xtag-total-run-finished>114</xtag-total-run-finished></td>
<td><xtag-total-run-started>117</xtag-total-run-started></td>
<td><xtag-total-run-finished>117</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
@ -726,8 +726,8 @@
</tr>
<tr>
<td><xtag-program-name>par</xtag-program-name></td>
<td><xtag-total-run-started>107</xtag-total-run-started></td>
<td><xtag-total-run-finished>107</xtag-total-run-finished></td>
<td><xtag-total-run-started>110</xtag-total-run-started></td>
<td><xtag-total-run-finished>110</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
@ -736,8 +736,8 @@
</tr>
<tr>
<td><xtag-program-name>trce</xtag-program-name></td>
<td><xtag-total-run-started>107</xtag-total-run-started></td>
<td><xtag-total-run-finished>107</xtag-total-run-finished></td>
<td><xtag-total-run-started>110</xtag-total-run-started></td>
<td><xtag-total-run-finished>110</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>
@ -746,8 +746,8 @@
</tr>
<tr>
<td><xtag-program-name>xst</xtag-program-name></td>
<td><xtag-total-run-started>211</xtag-total-run-started></td>
<td><xtag-total-run-finished>208</xtag-total-run-finished></td>
<td><xtag-total-run-started>212</xtag-total-run-started></td>
<td><xtag-total-run-finished>209</xtag-total-run-finished></td>
<td><xtag-total-error>0</xtag-total-error></td>
<td><xtag-total-fatal-error>0</xtag-total-fatal-error></td>
<td><xtag-total-internal-error>0</xtag-total-internal-error></td>

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@ -4,7 +4,7 @@ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Project Information
--------------------
ProjectID=3e658027d9514d018043b63a2e613df7
ProjectIteration=9
ProjectIteration=11
WebTalk Summary
----------------

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