sie-ceimtun/Examples/Beta1/logic/build/_xmsgs/map.xmsgs

<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
     by the Xilinx ISE software.  Any direct editing or
     changes made to this file may result in unpredictable
     behavior or data corruption.  It is strongly advised that
     users do not edit the contents of this file. -->
<messages>
<msg type="info" file="MapLib" num="562" delta="old" >No environment variables are currently set.
</msg>

<msg type="info" file="LIT" num="244" delta="old" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.
</msg>

</messages>
Uploaded the first Beta to test in the development group 2010-10-31 02:34:22 +03:00			`<?xml version="1.0" encoding="UTF-8"?>`
			`<!-- IMPORTANT: This is an internal file that has been generated`
			`by the Xilinx ISE software. Any direct editing or`
			`changes made to this file may result in unpredictable`
			`behavior or data corruption. It is strongly advised that`
			`users do not edit the contents of this file. -->`
			`<messages>`
Changed src in Beta with example to all 4 PWM at 100% 2010-10-31 05:27:00 +02:00			`<msg type="info" file="MapLib" num="562" delta="old" >No environment variables are currently set.`
Uploaded the first Beta to test in the development group 2010-10-31 02:34:22 +03:00			`</msg>`

Changed src in Beta with example to all 4 PWM at 100% 2010-10-31 05:27:00 +02:00			`<msg type="info" file="LIT" num="244" delta="old" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.`
Uploaded the first Beta to test in the development group 2010-10-31 02:34:22 +03:00			`</msg>`

			`</messages>`