sie-ceimtun/Examples/Beta1/logic/build/project_r.unroutes

Release 12.2 - par M.63c (lin64)
Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.

Sat Oct 30 21:34:01 2010

All signals are completely routed.
Uploaded the first Beta to test in the development group 2010-10-31 02:34:22 +03:00			`Release 12.2 - par M.63c (lin64)`
			`Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.`

Changed src in Beta with example to all 4 PWM at 100% 2010-10-31 05:27:00 +02:00			`Sat Oct 30 21:34:01 2010`
Uploaded the first Beta to test in the development group 2010-10-31 02:34:22 +03:00
			`All signals are completely routed.`