m1/case/: added rear panel with JTAG hole

m1/case/case.fpd

@@ -58,10 +58,79 @@ frame short {
 	line . __19 w
 }
 
-frame usb {
-	set Wusb = 8.5mm
+frame debug {
+	table
+	    { Wdbg, Hdbg }
+	    { 14.5mm, 9.5mm }
 
-	set Husb = 15.5mm
+	__0: vec @(Wdbg, Hdbg)
+	rect @ . w
+}
+
+frame dc {
+	table
+	    { Wdc, Hdc }
+	    { 9.4mm, 11.4mm }
+
+	__0: vec @(-Wdc, Hdc)
+	rect @ . w
+}
+
+frame ether {
+	table
+	    { Weth, Heth }
+	    { 16.5mm, 14mm }
+
+	__0: vec @(Weth, Heth)
+	rect @ . w
+}
+
+frame rgb {
+	set Rrgb = 6.3mm
+
+	__0: vec @(0mm, Rrgb)
+	circ @ . w
+}
+
+frame rear {
+	table
+	    { Irgbx, Irgby, Drgb }
+	    { 25.5mm, 14.5mm, 15mm }
+
+	table
+	    { Iethx, Iethy }
+	    { 67mm, 7mm }
+
+	table
+	    { Idcx, Idcy }
+	    { 14.8mm, 6.6mm }
+
+	table
+	    { Idbgx, Idbgy }
+	    { 88.1mm, 14.5mm }
+
+	loop if = 1, rear
+
+	__0: vec @(Irgbx, Irgby)
+	frame rgb .
+	__1: vec .(Drgb, 0mm)
+	frame rgb .
+	__2: vec .(Drgb, 0mm)
+	frame rgb .
+	__3: vec @(Iethx, Iethy)
+	frame ether .
+	__4: vec @(Ws, 0mm)
+	__5: vec .(-Idcx, Idcy)
+	frame dc .
+	__6: vec @(Idbgx, Idbgy)
+	frame debug .
+	frame short @
+}
+
+frame usb {
+	table
+	    { Wusb, Husb }
+	    { 8.5mm, 15.5mm }
 
 	__0: vec @(-Wusb, Husb)
 	rect . @ w
@@ -81,7 +150,9 @@ frame front {
 
 	table
 	    { Iusbx, Iusby, Dusb }
-	    { 18.5mm, 6.5mm+1.3mm, 12.5mm }
+	    { 18.5mm, 6.5mm+1.4mm, 12.5mm }
+
+	loop if = 1, front
 
 	__0: vec @(Ibutx, Ibuty)
 	frame but .
@@ -97,7 +168,7 @@ frame front {
 	frame short @
 }
 
-package "M1"
+package "M1-$part"
 unit mm
 
 table
@@ -110,4 +181,10 @@ table
     { H, Ws }
     { 36.5mm, 2*(Iox+Lox+Iix)+Lix }
 
+table
+    { part, front, rear }
+    { "front", 1, 0 }
+    { "rear", 0, 1 }
+
 frame front @
+frame rear @