mirror of
git://projects.qi-hardware.com/xburst-tools.git
synced 2025-04-21 12:27:27 +03:00
qi-move-cpu-specific-drivers-into-cpu-dir.patch
Signed-off-by: Andy Green <andy@openmoko.com>
This commit is contained in:
Andy Green
Andy Green
@@ -29,29 +29,35 @@ SECTIONS
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{
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. = 0x00000000;
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/* this is intended to take the first 4KBytes of stuff initially.
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* We have to make sure we have .rodata* in there for everything
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* because we do not compile PIC.
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/* this text section is magically pulled from the SD Card
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* and stored by the iRom at 0x0c000000, then it is jumped into
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* by the iRom. So we arrange our early parts needed at 0 in the
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* output file, but set to run at 0x0c000000+
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*/
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. = ALIGN(4);
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.text :
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.text 0x0c000000 : AT ( 0 )
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{
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src/cpu/s3c6410/start.o (.text .rodata* .data)
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src/lowlevel_init.o (.text .rodata* .data)
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src/cpu/s3c6410/start_qi.o (.text .rodata* .data)
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src/blink_led.o (.text .rodata* .data)
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src/cpu/s3c6410/start.o (.text .rodata* .data)
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src/cpu/s3c6410/start_qi.o (.text .rodata* .data)
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src/cpu/s3c6410/serial-s3c64xx.o (.text .rodata* .data)
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src/cpu/s3c6410/tla01.o (.text .rodata* .data)
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src/ctype.o (.text .rodata* .data)
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src/phase2.o (.text .rodata* .data)
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src/utils.o (.text .rodata* .data)
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}
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. = ALIGN(4);
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/* . = ALIGN(4);
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.everything_else ADDR (.text) + SIZEOF (.text) + 0x53000000 :
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AT ( ADDR (.text) + SIZEOF (.text) ) { *(.text .rodata* .data) }
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*/
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. = 0x53800000 ;
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/* . = 0x0c001900 ; */
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__bss_start = .;
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.bss_6410 (NOLOAD) :
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{
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* (.bss)
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}
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_end = .;
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}
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47
qiboot/src/cpu/s3c6410/serial-s3c64xx.c
Normal file
47
qiboot/src/cpu/s3c6410/serial-s3c64xx.c
Normal file
@@ -0,0 +1,47 @@
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/*
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* (C) Copyright 2007 OpenMoko, Inc.
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* Author: xiangfu liu <xiangfu@openmoko.org>
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*
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* Configuation settings for the FIC Neo GTA02 Linux GSM phone
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <qi.h>
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#include <s3c6410.h>
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/*
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* Output a single byte to the serial port.
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*/
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void serial_putc_s3c64xx(const int uart, const char c)
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{
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switch(uart)
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{
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case 0:
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while (!( UTRSTAT0_REG & 0x2 ))
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;
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UTXH0_REG = c;
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break;
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case 1:
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while (!( UTRSTAT1_REG & 0x2))
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;
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UTXH1_REG = c;
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break;
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default:
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break;
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}
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}
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@@ -141,11 +141,6 @@ _start_armboot:
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_TEXT_BASE:
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.word TEXT_BASE
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processor_id:
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.word 0
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.word 0x41129200 /* s3c2442 ID */
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.word 0x410fb760 /* s3c6410 ID */
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/*
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* These are defined in the board-specific linker script.
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*/
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@@ -311,12 +306,12 @@ start_code:
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mov r1, #0x0
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str r1, [r0, #INDEX_DMC_MEMC_CMD]
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check_dmc1_ready:
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1:
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ldr r1, [r0, #INDEX_DMC_MEMC_STATUS]
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mov r2, #0x3
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and r1, r1, r2
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cmp r1, #0x1
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bne check_dmc1_ready
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bne 1b
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nop
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ldr r0, =ELFIN_CLOCK_POWER_BASE @0x7e00f000
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@@ -336,12 +331,12 @@ check_dmc1_ready:
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orr r1, r1, r2
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str r1, [r0, #OTHERS_OFFSET]
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check_syncack:
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2:
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ldr r1, [r0, #OTHERS_OFFSET]
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ldr r2, =0xf00
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and r1, r1, r2
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cmp r1, #0xf00
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bne check_syncack
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bne 2b
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mov r1, #0xff00
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orr r1, r1, #0xff
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@@ -385,8 +380,8 @@ check_syncack:
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/* wait at least 200us to stablize all clock */
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mov r1, #0x10000
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1: subs r1, r1, #1
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bne 1b
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3: subs r1, r1, #1
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bne 3b
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ldr r1, [r0, #OTHERS_OFFSET]
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orr r1, r1, #0x20
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@@ -417,121 +412,14 @@ check_syncack:
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ldr r1, =0x1FFF
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str r1, [r0, #UDIVSLOT_OFFSET]
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ldr r1, =0x4f4f4f4f
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str r1, [r0, #UTXH_OFFSET] @'O'
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/* send out a char to say hello */
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ldr r1, =0x55
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str r1, [r0, #UTXH_OFFSET]
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#if 0
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/* Below code is for ARM926EJS and ARM1026EJS */
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.globl cleanDCache
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cleanDCache:
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mrc p15, 0, pc, c7, c10, 3 /* test/clean D-Cache */
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bne cleanDCache
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mov pc, lr
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.globl cleanFlushDCache
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cleanFlushDCache:
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mrc p15, 0, pc, c7, c14, 3 /* test/cleanflush D-Cache */
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bne cleanFlushDCache
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mov pc, lr
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.globl cleanFlushCache
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cleanFlushCache:
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mrc p15, 0, pc, c7, c14, 3 /* test/cleanflush D-Cache */
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bne cleanFlushCache
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mcr p15, 0, r0, c7, c5, 0 /* flush I-Cache */
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mov pc, lr
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.ltorg
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#endif
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#if 0
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/* enable only CPU peripheral block clocks we actually use */
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ldr r0, =0x4c00000c /* clkcon */
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ldr r1, =0x3f10 /* uart, pwm, gpio, nand, sdi clocks on */
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str r1, [r0]
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/* gpio UART2 init, H port */
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ldr r0, =0x56000070
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ldr r1, =0x001AAAAA
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str r1, [r0]
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/* enable KEEPACT(GPJ8) to make sure PMU keeps us alive */
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ldr r0, =0x56000000 /* GPJ base */
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ldr r1, [r0, #0xd0] /* GPJCON */
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orr r1, r1, #(1 << 16)
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str r1, [r0, #0xd0]
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ldr r1, [r0, #0xd4] /* GPJDAT */
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orr r1, r1, #(1 << 8)
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str r1, [r0, #0xd4]
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/* take sdram out of power down */
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ldr r0, =0x56000080 /* misccr */
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ldr r1, [ r0 ]
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bic r1, r1, #(S3C2410_MISCCR_nEN_SCLK0 | S3C2410_MISCCR_nEN_SCLK1 | S3C2410_MISCCR_nEN_SCLKE)
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str r1, [ r0 ]
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/* ensure signals stabalise */
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mov r1, #128
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1: subs r1, r1, #1
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bpl 1b
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bl cpu_init_crit
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/* ensure some refresh has happened */
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ldr r1, =0xfffff
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1: subs r1, r1, #1
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bpl 1b
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/* capture full EINT situation into gstatus 4 */
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ldr r0, =0x4A000000 /* SRCPND */
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ldr r1, [ r0 ]
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and r1, r1, #0xf
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ldr r0, =0x560000BC /* gstatus4 */
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str r1, [ r0 ]
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ldr r0, =0x560000A8 /* EINTPEND */
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ldr r1, [ r0 ]
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ldr r0, =0xfff0
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and r1, r1, r0
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ldr r0, =0x560000BC /* gstatus4 */
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ldr r0, [ r0 ]
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orr r1, r1, r0
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ldr r0, =0x560000BC /* gstatus4 */
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str r1, [ r0 ]
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/* test for resume */
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ldr r1, =0x560000B4 /* gstatus2 */
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ldr r0, [ r1 ]
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tst r0, #0x02 /* is this resume from power down */
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/* well, if it was, we are going to jump to
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* whatever address we stashed in gstatus3,
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* and gstatus4 will hold the wake interrupt
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* source for the OS to look at
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*/
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ldrne pc, [r1, #4]
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#endif
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/* >> CFG_VIDEO_LOGO_MAX_SIZE */
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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stack_setup:
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ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
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sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
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sub sp, r0, #12 /* leave 3 words for abort-stack */
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clear_bss:
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ldr r0, _bss_start /* find start of bss segment */
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ldr r1, _bss_end /* stop here */
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@@ -543,6 +431,14 @@ clbss_l:
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cmp r0, r1
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ble clbss_l
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/* we are going to jump into the C part of the init now */
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spin:
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#if 0
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ldr r0, =ELFIN_UART_CONSOLE_BASE
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ldr r1, =0x55
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push {r1}
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pop {r1}
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str r1, [r0, #UTXH_OFFSET] @'U'
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#endif
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b _steppingstone_done
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4:
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b 4b
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@@ -37,6 +37,8 @@ const struct board_api *boards[] = {
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struct board_api const * this_board;
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extern int is_jtag;
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#include <serial-s3c64xx.h>
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void start_qi(void)
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{
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int flag = 0;
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@@ -97,9 +99,8 @@ void start_qi(void)
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* jump to bootloader_second_phase() running from DRAM copy
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*/
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bootloader_second_phase();
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#if 0
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unhappy:
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while(1)
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;
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#endif
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}
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@@ -1,24 +1,25 @@
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#include <qi.h>
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#include <neo_tla01.h>
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#include <serial-s3c24xx.h>
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#include <ports-s3c24xx.h>
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#include <i2c-bitbang-s3c24xx.h>
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#include <serial-s3c64xx.h>
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//#include <ports-s3c24xx.h>
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//#include <i2c-bitbang-s3c24xx.h>
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#include <pcf50633.h>
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#define GTA03_DEBUG_UART 2
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#define GTA03_DEBUG_UART 0
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#define PCF50633_I2C_ADS 0x73
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static const struct board_variant board_variants[] = {
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[0] = {
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.name = "TLA01",
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.name = "SMDK",
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.machine_revision = 0x010,
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},
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};
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void port_init_tla01(void)
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{
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#if 0
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unsigned int * MPLLCON = (unsigned int *)0x4c000004;
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unsigned int * UPLLCON = (unsigned int *)0x4c000008;
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unsigned int * CLKDIVN = (unsigned int *)0x4c000014;
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@@ -135,28 +136,7 @@ void port_init_tla01(void)
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/* push DOWN1 (CPU Core rail) to 1.7V, allowing 533MHz */
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i2c_write_sync(&bb_s3c24xx, PCF50633_I2C_ADS, PCF50633_REG_DOWN1OUT,
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0x2b);
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/* change CPU clocking to 533MHz 1:4:8 */
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/* clock divide 1:4:8 - do it first */
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*CLKDIVN = 5;
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/* configure UPLL */
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*UPLLCON = ((88 << 12) + (4 << 4) + 2);
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/* Magic delay: Page 7-19, seven nops between UPLL and MPLL */
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asm __volatile__ (
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"nop\n"\
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"nop\n"\
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"nop\n"\
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"nop\n"\
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"nop\n"\
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"nop\n"\
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"nop\n"\
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);
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/* configure MPLL */
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*MPLLCON = ((169 << 12) + (2 << 4) + 1);
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serial_init_115200_s3c24xx(GTA03_DEBUG_UART, 66 /*MHz PCLK */);
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#endif
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}
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/**
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@@ -167,36 +147,7 @@ void port_init_tla01(void)
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int tla01_get_pcb_revision(void)
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{
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int n;
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u32 u;
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/* make B0 inputs */
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rGPBCON &= ~0x00000003;
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/* D8 and D9 inputs */
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rGPDCON &= ~0x000f0000;
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/* delay after changing pulldowns */
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u = rGPBDAT;
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u = rGPDDAT;
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/* read the version info */
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u = rGPBDAT;
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n = (u >> (0 - 0))& 0x001;
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u = rGPDDAT;
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n |= (u >> (8 -1)) & 0x002;
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n |= (u >> (9 - 2)) & 0x004;
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/*
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* when not being interrogated, all of the revision GPIO
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* are set to output
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*/
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/* make B0 high ouput */
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rGPBCON |= 0x00000001;
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/* D8 and D9 high ouputs */
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rGPDCON |= 0x00050000;
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return n;
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return 0;
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}
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const struct board_variant const * get_board_variant_tla01(void)
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@@ -212,7 +163,7 @@ int is_this_board_tla01(void)
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static void putc_tla01(char c)
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{
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serial_putc_s3c24xx(GTA03_DEBUG_UART, c);
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serial_putc_s3c64xx(GTA03_DEBUG_UART, c);
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}
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@@ -222,9 +173,9 @@ static void putc_tla01(char c)
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const struct board_api board_api_tla01 = {
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.name = "TLA01",
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.linux_machine_id = 1866,
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.linux_mem_start = 0x30000000,
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.linux_mem_start = 0x50000000,
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.linux_mem_size = (128 * 1024 * 1024),
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.linux_tag_placement = 0x30000000 + 0x100,
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.linux_tag_placement = 0x50000000 + 0x100,
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.get_board_variant = get_board_variant_tla01,
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.is_this_board = is_this_board_tla01,
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.port_init = port_init_tla01,
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