mirror of
git://projects.qi-hardware.com/xburst-tools.git
synced 2025-04-21 12:27:27 +03:00
qi-move-cpu-specific-drivers-into-cpu-dir.patch
Signed-off-by: Andy Green <andy@openmoko.com>
This commit is contained in:
@@ -141,11 +141,6 @@ _start_armboot:
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_TEXT_BASE:
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.word TEXT_BASE
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processor_id:
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.word 0
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.word 0x41129200 /* s3c2442 ID */
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.word 0x410fb760 /* s3c6410 ID */
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/*
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* These are defined in the board-specific linker script.
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*/
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@@ -311,12 +306,12 @@ start_code:
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mov r1, #0x0
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str r1, [r0, #INDEX_DMC_MEMC_CMD]
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check_dmc1_ready:
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1:
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ldr r1, [r0, #INDEX_DMC_MEMC_STATUS]
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mov r2, #0x3
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and r1, r1, r2
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cmp r1, #0x1
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bne check_dmc1_ready
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bne 1b
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nop
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ldr r0, =ELFIN_CLOCK_POWER_BASE @0x7e00f000
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@@ -336,12 +331,12 @@ check_dmc1_ready:
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orr r1, r1, r2
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str r1, [r0, #OTHERS_OFFSET]
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check_syncack:
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2:
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ldr r1, [r0, #OTHERS_OFFSET]
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ldr r2, =0xf00
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and r1, r1, r2
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cmp r1, #0xf00
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bne check_syncack
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bne 2b
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mov r1, #0xff00
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orr r1, r1, #0xff
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@@ -385,8 +380,8 @@ check_syncack:
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/* wait at least 200us to stablize all clock */
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mov r1, #0x10000
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1: subs r1, r1, #1
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bne 1b
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3: subs r1, r1, #1
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bne 3b
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ldr r1, [r0, #OTHERS_OFFSET]
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orr r1, r1, #0x20
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@@ -417,121 +412,14 @@ check_syncack:
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ldr r1, =0x1FFF
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str r1, [r0, #UDIVSLOT_OFFSET]
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ldr r1, =0x4f4f4f4f
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str r1, [r0, #UTXH_OFFSET] @'O'
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/* send out a char to say hello */
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ldr r1, =0x55
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str r1, [r0, #UTXH_OFFSET]
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#if 0
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/* Below code is for ARM926EJS and ARM1026EJS */
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.globl cleanDCache
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cleanDCache:
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mrc p15, 0, pc, c7, c10, 3 /* test/clean D-Cache */
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bne cleanDCache
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mov pc, lr
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.globl cleanFlushDCache
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cleanFlushDCache:
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mrc p15, 0, pc, c7, c14, 3 /* test/cleanflush D-Cache */
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bne cleanFlushDCache
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mov pc, lr
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.globl cleanFlushCache
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cleanFlushCache:
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mrc p15, 0, pc, c7, c14, 3 /* test/cleanflush D-Cache */
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bne cleanFlushCache
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mcr p15, 0, r0, c7, c5, 0 /* flush I-Cache */
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mov pc, lr
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.ltorg
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#endif
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#if 0
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/* enable only CPU peripheral block clocks we actually use */
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ldr r0, =0x4c00000c /* clkcon */
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ldr r1, =0x3f10 /* uart, pwm, gpio, nand, sdi clocks on */
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str r1, [r0]
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/* gpio UART2 init, H port */
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ldr r0, =0x56000070
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ldr r1, =0x001AAAAA
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str r1, [r0]
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/* enable KEEPACT(GPJ8) to make sure PMU keeps us alive */
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ldr r0, =0x56000000 /* GPJ base */
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ldr r1, [r0, #0xd0] /* GPJCON */
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orr r1, r1, #(1 << 16)
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str r1, [r0, #0xd0]
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ldr r1, [r0, #0xd4] /* GPJDAT */
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orr r1, r1, #(1 << 8)
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str r1, [r0, #0xd4]
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/* take sdram out of power down */
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ldr r0, =0x56000080 /* misccr */
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ldr r1, [ r0 ]
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bic r1, r1, #(S3C2410_MISCCR_nEN_SCLK0 | S3C2410_MISCCR_nEN_SCLK1 | S3C2410_MISCCR_nEN_SCLKE)
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str r1, [ r0 ]
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/* ensure signals stabalise */
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mov r1, #128
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1: subs r1, r1, #1
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bpl 1b
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bl cpu_init_crit
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/* ensure some refresh has happened */
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ldr r1, =0xfffff
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1: subs r1, r1, #1
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bpl 1b
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/* capture full EINT situation into gstatus 4 */
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ldr r0, =0x4A000000 /* SRCPND */
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ldr r1, [ r0 ]
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and r1, r1, #0xf
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ldr r0, =0x560000BC /* gstatus4 */
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str r1, [ r0 ]
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ldr r0, =0x560000A8 /* EINTPEND */
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ldr r1, [ r0 ]
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ldr r0, =0xfff0
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and r1, r1, r0
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ldr r0, =0x560000BC /* gstatus4 */
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ldr r0, [ r0 ]
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orr r1, r1, r0
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ldr r0, =0x560000BC /* gstatus4 */
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str r1, [ r0 ]
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/* test for resume */
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ldr r1, =0x560000B4 /* gstatus2 */
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ldr r0, [ r1 ]
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tst r0, #0x02 /* is this resume from power down */
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/* well, if it was, we are going to jump to
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* whatever address we stashed in gstatus3,
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* and gstatus4 will hold the wake interrupt
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* source for the OS to look at
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*/
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ldrne pc, [r1, #4]
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#endif
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/* >> CFG_VIDEO_LOGO_MAX_SIZE */
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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stack_setup:
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ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
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sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
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sub sp, r0, #12 /* leave 3 words for abort-stack */
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clear_bss:
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ldr r0, _bss_start /* find start of bss segment */
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ldr r1, _bss_end /* stop here */
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@@ -543,6 +431,14 @@ clbss_l:
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cmp r0, r1
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ble clbss_l
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/* we are going to jump into the C part of the init now */
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spin:
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#if 0
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ldr r0, =ELFIN_UART_CONSOLE_BASE
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ldr r1, =0x55
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push {r1}
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pop {r1}
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str r1, [r0, #UTXH_OFFSET] @'U'
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#endif
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b _steppingstone_done
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4:
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b 4b
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