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qi-move-cpu-specific-drivers-into-cpu-dir.patch

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Signed-off-by: Andy Green <andy@openmoko.com>
This commit is contained in:
Andy Green 2008-11-28 10:16:40 +00:00 committed by Andy Green
parent 007a6b20a7
commit 24a263998c
18 changed files with 218 additions and 1010 deletions
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2
qiboot/6410-partition-sd.sh
View File

@ -26,7 +26,7 @@ SIG=1
FDISK_SCRIPT=/tmp/_fds FDISK_SCRIPT=/tmp/_fds
if [ -z $1 -o -z $2 -o -z $3 ] ; then if [ -z "$1" -o -z "$2" -o -z "$3" ] ; then
echo "This formats a SD card for usage on SD Card boot" echo "This formats a SD card for usage on SD Card boot"
echo " on 6410 based systems" echo " on 6410 based systems"
echo echo

8
qiboot/Makefile
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@ -30,10 +30,10 @@ CFLAGS = -Wall -Werror -I $(INCLUDE) -g -c -Os -fno-strict-aliasing -mlong-calls
-fno-common -ffixed-r8 -msoft-float -fno-builtin -ffreestanding \ -fno-common -ffixed-r8 -msoft-float -fno-builtin -ffreestanding \
-march=armv4t -mno-thumb-interwork -Wstrict-prototypes \ -march=armv4t -mno-thumb-interwork -Wstrict-prototypes \
-DBUILD_HOST="${BUILD_HOST}" -DBUILD_VERSION="${BUILD_VERSION}" \ -DBUILD_HOST="${BUILD_HOST}" -DBUILD_VERSION="${BUILD_VERSION}" \
-DBUILD_DATE="${BUILD_DATE}" -DBUILD_DATE="${BUILD_DATE}" -DQI_CPU="${CPU}"
LDFLAGS = LDFLAGS =
S_SRCS = src/cpu/$(CPU)/start.S src/lowlevel_init.S S_SRCS = $(wildcard src/cpu/$(CPU)/*.S)
S_OBJS = $(patsubst %.S,%.o, $(S_SRCS)) S_OBJS = $(patsubst %.S,%.o, $(S_SRCS))
C_SRCS = $(wildcard src/*.c) \ C_SRCS = $(wildcard src/*.c) \
$(wildcard src/drivers/*.c) $(wildcard src/fs/*.c) \ $(wildcard src/drivers/*.c) $(wildcard src/fs/*.c) \
@ -44,6 +44,8 @@ SRCS = ${S_SRCS} ${C_SRCS}
OBJS = ${S_OBJS} ${C_OBJS} OBJS = ${S_OBJS} ${C_OBJS}
LIBS = -L${COMPILER_LIB_PATH} -lgcc LIBS = -L${COMPILER_LIB_PATH} -lgcc
OBJS = src/cpu/s3c6410/start.o src/cpu/s3c6410/start_qi.o src/cpu/s3c6410/serial-s3c64xx.o src/ctype.o src/utils.o src/cpu/s3c6410/tla01.o src/phase2.o
# GTA02 A5 and A6 U-Boot will eat these for DFU action # GTA02 A5 and A6 U-Boot will eat these for DFU action
UDFU_VID = 0x1d50 UDFU_VID = 0x1d50
UDFU_PID = 0x5119 UDFU_PID = 0x5119
@ -77,5 +79,5 @@ ${UDFU_IMAGE}:${OBJS} ${MKUDFU}
@$(OBJDUMP) -d ${TARGET} >${IMAGE}.dis @$(OBJDUMP) -d ${TARGET} >${IMAGE}.dis
clean: clean:
@rm -f src/*.o src/*~ include/*~ ${IMAGE_DIR}/* ${TARGET} ${UDFU_IMAGE} @rm -f src/*.o cpu/*/*.o cpu/*/*~ src/*~ src/drivers/*.o src/drivers/*~ include/*~ ${IMAGE_DIR}/* ${TARGET} ${UDFU_IMAGE}
@make clean -C $(TOOLS) @make clean -C $(TOOLS)

75
qiboot/include/s3c6410.h
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@ -45,6 +45,8 @@ typedef enum {
S3C64XX_UART2, S3C64XX_UART2,
} S3C64XX_UARTS_NR; } S3C64XX_UARTS_NR;
#define __REG(x) (*((unsigned int *)(x)))
//#include <s3c64x0.h> //#include <s3c64x0.h>
#endif #endif
@ -1306,79 +1308,6 @@ typedef enum {
/* include common stuff */ /* include common stuff */
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
static inline S3C64XX_MEMCTL * S3C64XX_GetBase_MEMCTL(void)
{
return (S3C64XX_MEMCTL *)(ELFIN_DMC0_BASE);
}
static inline S3C64XX_USB_HOST * S3C64XX_GetBase_USB_HOST(void)
{
return (S3C64XX_USB_HOST *)ELFIN_USB_HOST_BASE;
}
static inline S3C64XX_INTERRUPT * S3C64XX_GetBase_INTERRUPT(void)
{
return (S3C64XX_INTERRUPT *)ELFIN_VIC0_BASE_ADDR;
}
static inline S3C64XX_DMAS * S3C64XX_GetBase_DMAS(void)
{
return (S3C64XX_DMAS *)ELFIN_DMA_BASE;
}
static inline S3C64XX_CLOCK_POWER * S3C64XX_GetBase_CLOCK_POWER(void)
{
return (S3C64XX_CLOCK_POWER *)ELFIN_CLOCK_POWER_BASE;
}
static inline S3C64XX_LCD * S3C64XX_GetBase_LCD(void)
{
return (S3C64XX_LCD *)ELFIN_LCD_BASE;
}
/*
static inline S3C2410_NAND * S3C2410_GetBase_NAND(void)
{
return (S3C2410_NAND *)ELFIN_NAND_BASE;
}
*/
static inline S3C64XX_UART * S3C64XX_GetBase_UART(S3C64XX_UARTS_NR nr)
{
// return (S3C64XX_UART *)(ELFIN_UART_BASE + (nr * 0x4000));
return (S3C64XX_UART *)(ELFIN_UART_BASE + (nr*0x400));
}
static inline S3C64XX_TIMERS * S3C64XX_GetBase_TIMERS(void)
{
return (S3C64XX_TIMERS *)ELFIN_TIMER_BASE;
}
/*
static inline S3C64XX_USB_DEVICE * S3C64XX_GetBase_USB_DEVICE(void)
{
return (S3C64XX_USB_DEVICE *)ELFIN_USB_DEVICE_BASE;
}
*/
static inline S3C64XX_WATCHDOG * S3C64XX_GetBase_WATCHDOG(void)
{
return (S3C64XX_WATCHDOG *)ELFIN_WATCHDOG_BASE;
}
static inline S3C64XX_I2C * S3C64XX_GetBase_I2C(void)
{
return (S3C64XX_I2C *)ELFIN_I2C_BASE;
}
static inline S3C64XX_I2S * S3C64XX_GetBase_I2S(void)
{
return (S3C64XX_I2S *)ELFIN_I2S_BASE;
}
static inline S3C64XX_GPIO * S3C64XX_GetBase_GPIO(void)
{
return (S3C64XX_GPIO *)ELFIN_GPIO_BASE;
}
static inline S3C64XX_RTC * S3C64XX_GetBase_RTC(void)
{
return (S3C64XX_RTC *)ELFIN_RTC_BASE;
}
static inline S3C2410_ADC * S3C2410_GetBase_ADC(void)
{
return (S3C2410_ADC *)ELFIN_ADC_BASE;
}
static inline S3C64XX_SPI * S3C64XX_GetBase_SPI(void)
{
return (S3C64XX_SPI *)ELFIN_SPI_BASE;
}
#if 0 #if 0
static inline S3C2410_SDI * S3C2410_GetBase_SDI(void) static inline S3C2410_SDI * S3C2410_GetBase_SDI(void)
{ {

72
qiboot/include/serial-s3c64xx.h Normal file
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@ -0,0 +1,72 @@
/*
* (C) Copyright 2007 OpenMoko, Inc.
* Author: xiangfu liu <xiangfu@openmoko.org>
*
* Configuation settings for the FIC Neo GTA02 Linux GSM phone
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __SERIAL_S3C64XX_H__
#define __SERIAL_S3C64XX_H__
#define UART0 0
#define UART1 1
#define UART2 2
#define rGPHCON (*(volatile unsigned *)0x56000070) /*UART 0 Line control*/
#define rULCON0 (*(volatile unsigned *)0x50000000) /*UART 0 Line control*/
#define rUCON0 (*(volatile unsigned *)0x50000004) /*UART 0 Control*/
#define rUFCON0 (*(volatile unsigned *)0x50000008) /*UART 0 FIFO control*/
#define rUMCON0 (*(volatile unsigned *)0x5000000c) /*UART 0 Modem control*/
#define rUTRSTAT0 (*(volatile unsigned *)0x50000010) /*UART 0 Tx/Rx status*/
#define rUERSTAT0 (*(volatile unsigned *)0x50000014) /*UART 0 Rx error status*/
#define rUFSTAT0 (*(volatile unsigned *)0x50000018) /*UART 0 FIFO status*/
#define rUMSTAT0 (*(volatile unsigned *)0x5000001c) /*UART 0 Modem status*/
#define rUBRDIV0 (*(volatile unsigned *)0x50000028) /*UART 0 Baud rate divisor*/
#define rULCON1 (*(volatile unsigned *)0x50004000) /*UART 1 Line control*/
#define rUCON1 (*(volatile unsigned *)0x50004004) /*UART 1 Control*/
#define rUFCON1 (*(volatile unsigned *)0x50004008) /*UART 1 FIFO control*/
#define rUMCON1 (*(volatile unsigned *)0x5000400c) /*UART 1 Modem control*/
#define rUTRSTAT1 (*(volatile unsigned *)0x50004010) /*UART 1 Tx/Rx status*/
#define rUERSTAT1 (*(volatile unsigned *)0x50004014) /*UART 1 Rx error status*/
#define rUFSTAT1 (*(volatile unsigned *)0x50004018) /*UART 1 FIFO status*/
#define rUMSTAT1 (*(volatile unsigned *)0x5000401c) /*UART 1 Modem status*/
#define rUBRDIV1 (*(volatile unsigned *)0x50004028) /*UART 1 Baud rate divisor*/
#define rULCON2 (*(volatile unsigned *)0x50008000) /*UART 2 Line control*/
#define rUCON2 (*(volatile unsigned *)0x50008004) /*UART 2 Control*/
#define rUFCON2 (*(volatile unsigned *)0x50008008) /*UART 2 FIFO control*/
#define rUTRSTAT2 (*(volatile unsigned *)0x50008010) /*UART 2 Tx/Rx status*/
#define rUERSTAT2 (*(volatile unsigned *)0x50008014) /*UART 2 Rx error status*/
#define rUFSTAT2 (*(volatile unsigned *)0x50008018) /*UART 2 FIFO status*/
#define rUBRDIV2 (*(volatile unsigned *)0x50008028) /*UART 2 Baud rate divisor*/
#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000020)=(unsigned char)(ch)
#define RdURXH0() (*(volatile unsigned char *)0x50000024)
#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004020)=(unsigned char)(ch)
#define RdURXH1() (*(volatile unsigned char *)0x50004024)
#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008020)=(unsigned char)(ch)
#define RdURXH2() (*(volatile unsigned char *)0x50008024)
extern void serial_init_115200_s3c64xx(const int uart, const int pclk_MHz);
extern void serial_putc_s3c64xx(const int uart, const char c);
extern int puts(const char *string);
#endif

0
qiboot/src/drivers/i2c-bitbang-s3c24xx.c → qiboot/src/cpu/s3c2442/i2c-bitbang-s3c24xx.c
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0
qiboot/src/lowlevel_init.S → qiboot/src/cpu/s3c2442/lowlevel_init.S
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2
qiboot/src/cpu/s3c2442/qi.lds
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@ -42,7 +42,7 @@ SECTIONS
src/cpu/s3c2442/start_qi.o (.text .rodata* .data) src/cpu/s3c2442/start_qi.o (.text .rodata* .data)
src/blink_led.o (.text .rodata* .data) src/blink_led.o (.text .rodata* .data)
src/cpu/s3c2442/nand_read.o (.text .rodata* .data) src/cpu/s3c2442/nand_read.o (.text .rodata* .data)
src/drivers/serial-s3c24xx.o (.text .rodata* .data) src/cpu/s3c2442/serial-s3c24xx.o (.text .rodata* .data)
} }
. = ALIGN(4); . = ALIGN(4);

0
qiboot/src/drivers/s3c24xx-mci.c → qiboot/src/cpu/s3c2442/s3c24xx-mci.c
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0
qiboot/src/drivers/serial-s3c24xx.c → qiboot/src/cpu/s3c2442/serial-s3c24xx.c
View File

22
qiboot/src/cpu/s3c6410/qi.lds
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@ -29,29 +29,35 @@ SECTIONS
{ {
. = 0x00000000; . = 0x00000000;
/* this is intended to take the first 4KBytes of stuff initially. /* this text section is magically pulled from the SD Card
* We have to make sure we have .rodata* in there for everything * and stored by the iRom at 0x0c000000, then it is jumped into
* because we do not compile PIC. * by the iRom. So we arrange our early parts needed at 0 in the
* output file, but set to run at 0x0c000000+
*/ */
. = ALIGN(4); .text 0x0c000000 : AT ( 0 )
.text :
{ {
src/cpu/s3c6410/start.o (.text .rodata* .data) src/cpu/s3c6410/start.o (.text .rodata* .data)
src/lowlevel_init.o (.text .rodata* .data)
src/cpu/s3c6410/start_qi.o (.text .rodata* .data) src/cpu/s3c6410/start_qi.o (.text .rodata* .data)
src/blink_led.o (.text .rodata* .data) src/cpu/s3c6410/serial-s3c64xx.o (.text .rodata* .data)
src/cpu/s3c6410/tla01.o (.text .rodata* .data)
src/ctype.o (.text .rodata* .data)
src/phase2.o (.text .rodata* .data)
src/utils.o (.text .rodata* .data)
} }
. = ALIGN(4); /* . = ALIGN(4);
.everything_else ADDR (.text) + SIZEOF (.text) + 0x53000000 : .everything_else ADDR (.text) + SIZEOF (.text) + 0x53000000 :
AT ( ADDR (.text) + SIZEOF (.text) ) { *(.text .rodata* .data) } AT ( ADDR (.text) + SIZEOF (.text) ) { *(.text .rodata* .data) }
*/
. = 0x53800000 ; . = 0x53800000 ;
/* . = 0x0c001900 ; */
__bss_start = .; __bss_start = .;
.bss_6410 (NOLOAD) : .bss_6410 (NOLOAD) :
{ {
* (.bss) * (.bss)
} }
_end = .; _end = .;
} }

47
qiboot/src/cpu/s3c6410/serial-s3c64xx.c Normal file
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@ -0,0 +1,47 @@
/*
* (C) Copyright 2007 OpenMoko, Inc.
* Author: xiangfu liu <xiangfu@openmoko.org>
*
* Configuation settings for the FIC Neo GTA02 Linux GSM phone
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <qi.h>
#include <s3c6410.h>
/*
* Output a single byte to the serial port.
*/
void serial_putc_s3c64xx(const int uart, const char c)
{
switch(uart)
{
case 0:
while (!( UTRSTAT0_REG & 0x2 ))
;
UTXH0_REG = c;
break;
case 1:
while (!( UTRSTAT1_REG & 0x2))
;
UTXH1_REG = c;
break;
default:
break;
}
}

138
qiboot/src/cpu/s3c6410/start.S
View File

@ -141,11 +141,6 @@ _start_armboot:
_TEXT_BASE: _TEXT_BASE:
.word TEXT_BASE .word TEXT_BASE
processor_id:
.word 0
.word 0x41129200 /* s3c2442 ID */
.word 0x410fb760 /* s3c6410 ID */
/* /*
* These are defined in the board-specific linker script. * These are defined in the board-specific linker script.
*/ */
@ -311,12 +306,12 @@ start_code:
mov r1, #0x0 mov r1, #0x0
str r1, [r0, #INDEX_DMC_MEMC_CMD] str r1, [r0, #INDEX_DMC_MEMC_CMD]
check_dmc1_ready: 1:
ldr r1, [r0, #INDEX_DMC_MEMC_STATUS] ldr r1, [r0, #INDEX_DMC_MEMC_STATUS]
mov r2, #0x3 mov r2, #0x3
and r1, r1, r2 and r1, r1, r2
cmp r1, #0x1 cmp r1, #0x1
bne check_dmc1_ready bne 1b
nop nop
ldr r0, =ELFIN_CLOCK_POWER_BASE @0x7e00f000 ldr r0, =ELFIN_CLOCK_POWER_BASE @0x7e00f000
@ -336,12 +331,12 @@ check_dmc1_ready:
orr r1, r1, r2 orr r1, r1, r2
str r1, [r0, #OTHERS_OFFSET] str r1, [r0, #OTHERS_OFFSET]
check_syncack: 2:
ldr r1, [r0, #OTHERS_OFFSET] ldr r1, [r0, #OTHERS_OFFSET]
ldr r2, =0xf00 ldr r2, =0xf00
and r1, r1, r2 and r1, r1, r2
cmp r1, #0xf00 cmp r1, #0xf00
bne check_syncack bne 2b
mov r1, #0xff00 mov r1, #0xff00
orr r1, r1, #0xff orr r1, r1, #0xff
@ -385,8 +380,8 @@ check_syncack:
/* wait at least 200us to stablize all clock */ /* wait at least 200us to stablize all clock */
mov r1, #0x10000 mov r1, #0x10000
1: subs r1, r1, #1 3: subs r1, r1, #1
bne 1b bne 3b
ldr r1, [r0, #OTHERS_OFFSET] ldr r1, [r0, #OTHERS_OFFSET]
orr r1, r1, #0x20 orr r1, r1, #0x20
@ -417,121 +412,14 @@ check_syncack:
ldr r1, =0x1FFF ldr r1, =0x1FFF
str r1, [r0, #UDIVSLOT_OFFSET] str r1, [r0, #UDIVSLOT_OFFSET]
ldr r1, =0x4f4f4f4f
str r1, [r0, #UTXH_OFFSET] @'O'
/* send out a char to say hello */
ldr r1, =0x55
str r1, [r0, #UTXH_OFFSET]
#if 0
/* Below code is for ARM926EJS and ARM1026EJS */
.globl cleanDCache
cleanDCache:
mrc p15, 0, pc, c7, c10, 3 /* test/clean D-Cache */
bne cleanDCache
mov pc, lr
.globl cleanFlushDCache
cleanFlushDCache:
mrc p15, 0, pc, c7, c14, 3 /* test/cleanflush D-Cache */
bne cleanFlushDCache
mov pc, lr
.globl cleanFlushCache
cleanFlushCache:
mrc p15, 0, pc, c7, c14, 3 /* test/cleanflush D-Cache */
bne cleanFlushCache
mcr p15, 0, r0, c7, c5, 0 /* flush I-Cache */
mov pc, lr
.ltorg
#endif
#if 0
/* enable only CPU peripheral block clocks we actually use */
ldr r0, =0x4c00000c /* clkcon */
ldr r1, =0x3f10 /* uart, pwm, gpio, nand, sdi clocks on */
str r1, [r0]
/* gpio UART2 init, H port */
ldr r0, =0x56000070
ldr r1, =0x001AAAAA
str r1, [r0]
/* enable KEEPACT(GPJ8) to make sure PMU keeps us alive */
ldr r0, =0x56000000 /* GPJ base */
ldr r1, [r0, #0xd0] /* GPJCON */
orr r1, r1, #(1 << 16)
str r1, [r0, #0xd0]
ldr r1, [r0, #0xd4] /* GPJDAT */
orr r1, r1, #(1 << 8)
str r1, [r0, #0xd4]
/* take sdram out of power down */
ldr r0, =0x56000080 /* misccr */
ldr r1, [ r0 ]
bic r1, r1, #(S3C2410_MISCCR_nEN_SCLK0 | S3C2410_MISCCR_nEN_SCLK1 | S3C2410_MISCCR_nEN_SCLKE)
str r1, [ r0 ]
/* ensure signals stabalise */
mov r1, #128
1: subs r1, r1, #1
bpl 1b
bl cpu_init_crit
/* ensure some refresh has happened */
ldr r1, =0xfffff
1: subs r1, r1, #1
bpl 1b
/* capture full EINT situation into gstatus 4 */
ldr r0, =0x4A000000 /* SRCPND */
ldr r1, [ r0 ]
and r1, r1, #0xf
ldr r0, =0x560000BC /* gstatus4 */
str r1, [ r0 ]
ldr r0, =0x560000A8 /* EINTPEND */
ldr r1, [ r0 ]
ldr r0, =0xfff0
and r1, r1, r0
ldr r0, =0x560000BC /* gstatus4 */
ldr r0, [ r0 ]
orr r1, r1, r0
ldr r0, =0x560000BC /* gstatus4 */
str r1, [ r0 ]
/* test for resume */
ldr r1, =0x560000B4 /* gstatus2 */
ldr r0, [ r1 ]
tst r0, #0x02 /* is this resume from power down */
/* well, if it was, we are going to jump to
* whatever address we stashed in gstatus3,
* and gstatus4 will hold the wake interrupt
* source for the OS to look at
*/
ldrne pc, [r1, #4]
#endif
/* >> CFG_VIDEO_LOGO_MAX_SIZE */ /* >> CFG_VIDEO_LOGO_MAX_SIZE */
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
sub sp, r0, #12 /* leave 3 words for abort-stack */ sub sp, r0, #12 /* leave 3 words for abort-stack */
clear_bss: clear_bss:
ldr r0, _bss_start /* find start of bss segment */ ldr r0, _bss_start /* find start of bss segment */
ldr r1, _bss_end /* stop here */ ldr r1, _bss_end /* stop here */
@ -543,6 +431,14 @@ clbss_l:
cmp r0, r1 cmp r0, r1
ble clbss_l ble clbss_l
/* we are going to jump into the C part of the init now */ #if 0
spin: ldr r0, =ELFIN_UART_CONSOLE_BASE
ldr r1, =0x55
push {r1}
pop {r1}
str r1, [r0, #UTXH_OFFSET] @'U'
#endif
b _steppingstone_done b _steppingstone_done
4:
b 4b

7
qiboot/src/cpu/s3c6410/start_qi.c
View File

@ -37,6 +37,8 @@ const struct board_api *boards[] = {
struct board_api const * this_board; struct board_api const * this_board;
extern int is_jtag; extern int is_jtag;
#include <serial-s3c64xx.h>
void start_qi(void) void start_qi(void)
{ {
int flag = 0; int flag = 0;
@ -97,9 +99,8 @@ void start_qi(void)
* jump to bootloader_second_phase() running from DRAM copy * jump to bootloader_second_phase() running from DRAM copy
*/ */
bootloader_second_phase(); bootloader_second_phase();
#if 0
unhappy:
while(1) while(1)
; ;
#endif
} }

71
qiboot/src/cpu/s3c6410/tla01.c
View File

@ -1,24 +1,25 @@
#include <qi.h> #include <qi.h>
#include <neo_tla01.h> #include <neo_tla01.h>
#include <serial-s3c24xx.h> #include <serial-s3c64xx.h>
#include <ports-s3c24xx.h> //#include <ports-s3c24xx.h>
#include <i2c-bitbang-s3c24xx.h> //#include <i2c-bitbang-s3c24xx.h>
#include <pcf50633.h> #include <pcf50633.h>
#define GTA03_DEBUG_UART 2 #define GTA03_DEBUG_UART 0
#define PCF50633_I2C_ADS 0x73 #define PCF50633_I2C_ADS 0x73
static const struct board_variant board_variants[] = { static const struct board_variant board_variants[] = {
[0] = { [0] = {
.name = "TLA01", .name = "SMDK",
.machine_revision = 0x010, .machine_revision = 0x010,
}, },
}; };
void port_init_tla01(void) void port_init_tla01(void)
{ {
#if 0
unsigned int * MPLLCON = (unsigned int *)0x4c000004; unsigned int * MPLLCON = (unsigned int *)0x4c000004;
unsigned int * UPLLCON = (unsigned int *)0x4c000008; unsigned int * UPLLCON = (unsigned int *)0x4c000008;
unsigned int * CLKDIVN = (unsigned int *)0x4c000014; unsigned int * CLKDIVN = (unsigned int *)0x4c000014;
@ -135,28 +136,7 @@ void port_init_tla01(void)
/* push DOWN1 (CPU Core rail) to 1.7V, allowing 533MHz */ /* push DOWN1 (CPU Core rail) to 1.7V, allowing 533MHz */
i2c_write_sync(&bb_s3c24xx, PCF50633_I2C_ADS, PCF50633_REG_DOWN1OUT, i2c_write_sync(&bb_s3c24xx, PCF50633_I2C_ADS, PCF50633_REG_DOWN1OUT,
0x2b); 0x2b);
#endif
/* change CPU clocking to 533MHz 1:4:8 */
/* clock divide 1:4:8 - do it first */
*CLKDIVN = 5;
/* configure UPLL */
*UPLLCON = ((88 << 12) + (4 << 4) + 2);
/* Magic delay: Page 7-19, seven nops between UPLL and MPLL */
asm __volatile__ (
"nop\n"\
"nop\n"\
"nop\n"\
"nop\n"\
"nop\n"\
"nop\n"\
"nop\n"\
);
/* configure MPLL */
*MPLLCON = ((169 << 12) + (2 << 4) + 1);
serial_init_115200_s3c24xx(GTA03_DEBUG_UART, 66 /*MHz PCLK */);
} }
/** /**
@ -167,36 +147,7 @@ void port_init_tla01(void)
int tla01_get_pcb_revision(void) int tla01_get_pcb_revision(void)
{ {
int n; return 0;
u32 u;
/* make B0 inputs */
rGPBCON &= ~0x00000003;
/* D8 and D9 inputs */
rGPDCON &= ~0x000f0000;
/* delay after changing pulldowns */
u = rGPBDAT;
u = rGPDDAT;
/* read the version info */
u = rGPBDAT;
n = (u >> (0 - 0))& 0x001;
u = rGPDDAT;
n |= (u >> (8 -1)) & 0x002;
n |= (u >> (9 - 2)) & 0x004;
/*
* when not being interrogated, all of the revision GPIO
* are set to output
*/
/* make B0 high ouput */
rGPBCON |= 0x00000001;
/* D8 and D9 high ouputs */
rGPDCON |= 0x00050000;
return n;
} }
const struct board_variant const * get_board_variant_tla01(void) const struct board_variant const * get_board_variant_tla01(void)
@ -212,7 +163,7 @@ int is_this_board_tla01(void)
static void putc_tla01(char c) static void putc_tla01(char c)
{ {
serial_putc_s3c24xx(GTA03_DEBUG_UART, c); serial_putc_s3c64xx(GTA03_DEBUG_UART, c);
} }
@ -222,9 +173,9 @@ static void putc_tla01(char c)
const struct board_api board_api_tla01 = { const struct board_api board_api_tla01 = {
.name = "TLA01", .name = "TLA01",
.linux_machine_id = 1866, .linux_machine_id = 1866,
.linux_mem_start = 0x30000000, .linux_mem_start = 0x50000000,
.linux_mem_size = (128 * 1024 * 1024), .linux_mem_size = (128 * 1024 * 1024),
.linux_tag_placement = 0x30000000 + 0x100, .linux_tag_placement = 0x50000000 + 0x100,
.get_board_variant = get_board_variant_tla01, .get_board_variant = get_board_variant_tla01,
.is_this_board = is_this_board_tla01, .is_this_board = is_this_board_tla01,
.port_init = port_init_tla01, .port_init = port_init_tla01,

428
qiboot/src/gta02/gta02.c
View File

@ -1,428 +0,0 @@
/*
* (C) Copyright 2007 OpenMoko, Inc.
* Author: Andy Green <andy@openmoko.com>
*
* (port_init_gta02 came out of Openmoko U-Boot)
*
* Configuation settings for the OPENMOKO Neo GTA02 Linux GSM phone
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <qi.h>
#include <neo_gta02.h>
#include <serial-s3c24xx.h>
#include <ports-s3c24xx.h>
#include <i2c-bitbang-s3c24xx.h>
#include <pcf50633.h>
#include <glamo-init.h>
#define GTA02_DEBUG_UART 2
#define PCF50633_I2C_ADS 0x73
struct pcf50633_init {
u8 index;
u8 value;
};
const struct pcf50633_init pcf50633_init[] = {
{ PCF50633_REG_OOCWAKE, 0xd3 }, /* wake from ONKEY,EXTON!,RTC,USB,ADP */
{ PCF50633_REG_OOCTIM1, 0xaa }, /* debounce 14ms everything */
{ PCF50633_REG_OOCTIM2, 0x4a },
{ PCF50633_REG_OOCMODE, 0x55 },
{ PCF50633_REG_OOCCTL, 0x47 },
{ PCF50633_REG_SVMCTL, 0x08 }, /* 3.10V SYS voltage thresh. */
{ PCF50633_REG_BVMCTL, 0x02 }, /* 2.80V BAT voltage thresh. */
{ PCF50633_REG_AUTOENA, 0x01 }, /* always on */
{ PCF50633_REG_DOWN1OUT, 0x1b }, /* 1.3V (0x1b * .025V + 0.625V) */
{ PCF50633_REG_DOWN1ENA, 0x02 }, /* enabled if GPIO1 = HIGH */
{ PCF50633_REG_HCLDOOUT, 21 }, /* 3.0V (21 * 0.1V + 0.9V) */
{ PCF50633_REG_HCLDOENA, 0x01 }, /* ON by default*/
{ PCF50633_REG_INT1M, 0x00 },
{ PCF50633_REG_INT2M, 0x00 },
{ PCF50633_REG_INT3M, 0x00 },
{ PCF50633_REG_INT4M, 0x00 },
{ PCF50633_REG_INT5M, 0x00 },
{ PCF50633_REG_MBCC2, 0x28 }, /* Vbatconid=2.7V, Vmax=4.20V */
{ PCF50633_REG_MBCC3, 0x19 }, /* 25/255 == 98mA pre-charge */
{ PCF50633_REG_MBCC4, 0xff }, /* 255/255 == 1A adapter fast */
{ PCF50633_REG_MBCC5, 0x19 }, /* 25/255 == 98mA soft-start usb fast */
{ PCF50633_REG_MBCC6, 0x00 }, /* cutoff current 1/32 * Ichg */
{ PCF50633_REG_MBCC7, 0x00 }, /* 1.6A max bat curr, USB 100mA */
{ PCF50633_REG_MBCC8, 0x00 },
{ PCF50633_REG_MBCC1, 0xff }, /* chgena */
{ PCF50633_REG_BBCCTL, 0x19 }, /* 3V, 200uA, on */
{ PCF50633_REG_OOCSHDWN, 0x04 }, /* defeat 8s death from lowsys on A5 */
};
static const struct board_variant board_variants[] = {
[0] = {
.name = "A5 PCB",
.machine_revision = 0x350,
},
[1] = {
.name = "A6 PCB",
.machine_revision = 0x360,
}
};
void port_init_gta02(void)
{
#if 0
unsigned int * MPLLCON = (unsigned int *)0x4c000004;
unsigned int * UPLLCON = (unsigned int *)0x4c000008;
unsigned int * CLKDIVN = (unsigned int *)0x4c000014;
#endif
int n;
//CAUTION:Follow the configuration order for setting the ports.
// 1) setting value(GPnDAT)
// 2) setting control register (GPnCON)
// 3) configure pull-up resistor(GPnUP)
/* 32bit data bus configuration */
/*
* === PORT A GROUP
* Ports : GPA22 GPA21 GPA20 GPA19 GPA18 GPA17 GPA16 GPA15 GPA14 GPA13 GPA12
* Signal : nFCE nRSTOUT nFRE nFWE ALE CLE nGCS5 nGCS4 nGCS3 nGCS2 nGCS1
* Binary : 1 1 1 , 1 1 1 1 , 1 1 1 1
* Ports : GPA11 GPA10 GPA9 GPA8 GPA7 GPA6 GPA5 GPA4 GPA3 GPA2 GPA1 GPA0
* Signal : ADDR26 ADDR25 ADDR24 ADDR23 ADDR22 ADDR21 ADDR20 ADDR19 ADDR18 ADDR17 ADDR16 ADDR0
* Binary : 1 1 1 1 , 1 1 1 1 , 1 1 1 1
*/
rGPACON = 0x007E5FFF;
rGPADAT = 0x00000000;
/*
* ===* PORT B GROUP
* Ports : GPB10 GPB9 GPB8 GPB7 GPB6 GPB5 GPB4 GPB3 GPB2 GPB1 GPB0
* Signal : nXDREQ0 nXDACK0 nXDREQ1 nXDACK1 nSS_KBD nDIS_OFF L3CLOCK L3DATA L3MODE nIrDATXDEN Keyboard
* Setting: INPUT OUTPUT INPUT OUTPUT INPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT
* Binary : 00 , 01 00 , 01 00 , 01 01 , 01 01 , 01 01
*/
rGPBCON = 0x00155555;
rGPBUP = 0x000007FF;
rGPBDAT = 0x00000000;
/*
* === PORT C GROUP
* Ports : GPC15 GPC14 GPC13 GPC12 GPC11 GPC10 GPC9 GPC8 GPC7 GPC6 GPC5 GPC4 GPC3 GPC2 GPC1 GPC0
* Signal : VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 LCDVF2 LCDVF1 LCDVF0 VM VFRAME VLINE VCLK LEND
* Binary : 10 10 , 10 10 , 10 10 , 10 10 , 10 10 , 10 10 , 10 10 , 10 10
*/
rGPCCON = 0x55555155;
rGPCUP = 0x0000FFFF & ~(1 << 5);
rGPCDAT = (1 << 13) | (1 << 15); /* index detect -> hi */
/*
* === PORT D GROUP
* Ports : GPD15 GPD14 GPD13 GPD12 GPD11 GPD10 GPD9 GPD8 GPD7 GPD6 GPD5 GPD4 GPD3 GPD2 GPD1 GPD0
* Signal : VD23 VD22 VD21 VD20 VD19 VD18 VD17 VD16 VD15 VD14 VD13 VD12 VD11 VD10 VD9 VD8
* Binary : 10 10 , 10 10 , 10 10 , 10 10 , 10 10 , 10 10 , 10 10 ,10 10
*/
rGPDCON = 0x55555555;
rGPDUP = 0x0000FFFF;
rGPDDAT = (1 << 0) | (1 << 3) | (1 << 4); /* index detect -> hi */
/*
* === PORT E GROUP
* Ports : GPE15 GPE14 GPE13 GPE12 GPE11 GPE10 GPE9 GPE8 GPE7 GPE6 GPE5 GPE4
* Signal : IICSDA IICSCL SPICLK SPIMOSI SPIMISO SDDATA3 SDDATA2 SDDATA1 SDDATA0 SDCMD SDCLK I2SSDO
* Binary : 10 10 , 10 10 , 10 10 , 10 10 , 10 10 , 10 10 ,
* -------------------------------------------------------------------------------------------------------
* Ports : GPE3 GPE2 GPE1 GPE0
* Signal : I2SSDI CDCLK I2SSCLK I2SLRCK
* Binary : 10 10 , 10 10
*/
rGPECON = 0xAAAAAAAA;
rGPEUP = 0x0000FFFF & ~(1 << 11);
rGPEDAT = 0x00000000;
/*
* === PORT F GROUP
* Ports : GPF7 GPF6 GPF5 GPF4 GPF3 GPF2 GPF1 GPF0
* Signal : nLED_8 nLED_4 nLED_2 nLED_1 nIRQ_PCMCIA EINT2 KBDINT EINT0
* Setting: Output Output Output Output EINT3 EINT2 EINT1 EINT0
* Binary : 01 01 , 01 01 , 10 10 , 10 10
*/
/* pulldown on GPF03: TP-4705+debug - debug conn will float */
rGPFCON = 0x0000AAAA;
rGPFUP = 0x000000FF & ~(1 << 3);
rGPFDAT = 0x00000000;
/*
* === PORT G GROUP
* Ports : GPG15 GPG14 GPG13 GPG12 GPG11 GPG10 GPG9 GPG8 GPG7 GPG6
* Signal : nYPON YMON nXPON XMON EINT19 DMAMODE1 DMAMODE0 DMASTART KBDSPICLK KBDSPIMOSI
* Setting: nYPON YMON nXPON XMON EINT19 Output Output Output SPICLK1 SPIMOSI1
* Binary : 11 11 , 11 11 , 10 01 , 01 01 , 11 11
* -----------------------------------------------------------------------------------------
* Ports : GPG5 GPG4 GPG3 GPG2 GPG1 GPG0
* Signal : KBDSPIMISO LCD_PWREN EINT11 nSS_SPI IRQ_LAN IRQ_PCMCIA
* Setting: SPIMISO1 LCD_PWRDN EINT11 nSS0 EINT9 EINT8
* Binary : 11 11 , 10 11 , 10 10
*/
rGPGCON = 0x01AAFE79;
rGPGUP = 0x0000FFFF;
rGPGDAT = 0x00000000;
/*
* === PORT H GROUP
* Ports : GPH10 GPH9 GPH8 GPH7 GPH6 GPH5 GPH4 GPH3 GPH2 GPH1 GPH0
* Signal : CLKOUT1 CLKOUT0 UCLK RXD2 TXD2 RXD1 TXD1 RXD0 TXD0 nRTS0 nCTS0
* Binary : 10 , 10 10 , 11 11 , 10 10 , 10 10 , 10 10
*/
/* pulldown on GPH08: UEXTCLK, just floats!
* pulldown GPH0 -- nCTS0 / RTS_MODEM -- floats when GSM off
* pulldown GPH3 -- RXD[0] / TX_MODEM -- floats when GSM off
*/
rGPHCON = 0x001AAAAA;
rGPHUP = 0x000007FF & ~(1 << 8) & ~(1 << 0) & ~(1 << 3);
rGPHDAT = 0x00000000;
/* pulldown on GPJ00: input, just floats! */
/* pulldown on GPJ07: WLAN module WLAN_GPIO0, no ext pull */
rGPJCON = 0x1551544;
rGPJUP = 0x1ffff & ~(1 << 0) & ~(1 << 7);
rGPJDAT = 0x00000100;
rGPJDAT |= (1 << 4) | (1 << 6);
/* Set GPJ4 to high (nGSM_EN) */
/* Set GPJ6 to high (nDL_GSM) */
rGPJDAT &= ~(1 << 5); /* Set GPJ5 to low 3D RST */
/* leaving Glamo forced to Reset# active here killed
* U-Boot when you touched the memory region
*/
rGPJDAT |= (1 << 5); /* Set GPJ5 to high 3D RST */
/*
* We have to talk to the PMU a little bit
*/
for (n = 0; n < ARRAY_SIZE(pcf50633_init); n++)
i2c_write_sync(&bb_s3c24xx, PCF50633_I2C_ADS,
pcf50633_init[n].index, pcf50633_init[n].value);
#if 0
/* change CPU clocking to 400MHz 1:4:8 */
/* clock divide 1:4:8 - do it first */
*CLKDIVN = 5;
/* configure UPLL */
*UPLLCON = ((88 << 12) + (4 << 4) + 2);
/* Magic delay: Page 7-19, seven nops between UPLL and MPLL */
asm __volatile__ (
"nop\n"\
"nop\n"\
"nop\n"\
"nop\n"\
"nop\n"\
"nop\n"\
"nop\n"\
);
/* configure MPLL */
*MPLLCON = ((42 << 12) + (1 << 4) + 0);
/* get debug UART working at 115kbps */
serial_init_115200_s3c24xx(GTA02_DEBUG_UART, 50 /* 50MHz PCLK */);
#else
serial_init_115200_s3c24xx(GTA02_DEBUG_UART, 33 /* 33MHz PCLK */);
#endif
/* we're going to use Glamo for SD Card access, so we need to init the
* evil beast
*/
glamo_core_init();
}
/**
* returns PCB revision information in b9,b8 and b2,b1,b0
* Pre-GTA02 A6 returns 0x000
* GTA02 A6 returns 0x001
*/
int gta02_get_pcb_revision(void)
{
int n;
u32 u;
/* make C13 and C15 pulled-down inputs */
rGPCCON &= ~0xcc000000;
rGPCUP &= ~((1 << 13) | (1 << 15));
/* D0, D3 and D4 pulled-down inputs */
rGPDCON &= ~0x000003c3;
rGPDUP &= ~((1 << 0) | (1 << 3) | (1 << 4));
/* delay after changing pulldowns */
u = rGPCDAT;
u = rGPDDAT;
/* read the version info */
u = rGPCDAT;
n = (u >> (13 - 0)) & 0x001;
n |= (u >> (15 - 1)) & 0x002;
u = rGPDDAT;
n |= (u << (0 + 2)) & 0x004;
n |= (u << (8 - 3)) & 0x100;
n |= (u << (9 - 4)) & 0x200;
/*
* when not being interrogated, all of the revision GPIO
* are set to output HIGH without pulldown so no current flows
* if they are NC or pulled up.
*/
/* make C13 and C15 high ouputs with no pulldowns */
rGPCCON |= 0x44000000;
rGPCUP |= (1 << 13) | (1 << 15);
rGPCDAT |= (1 << 13) | (1 << 15);
/* D0, D3 and D4 high ouputs with no pulldowns */
rGPDCON |= 0x00000141;
rGPDUP |= (1 << 0) | (1 << 3) | (1 << 4);
rGPDDAT |= (1 << 0) | (1 << 3) | (1 << 4);
n &= 1;
return n;
}
int sd_card_init_gta02(void)
{
extern int mmc_init(int verbose);
return mmc_init(1);
}
int sd_card_block_read_gta02(unsigned char * buf, unsigned long start512,
int blocks512)
{
unsigned long mmc_bread(int dev_num, unsigned long blknr, unsigned long blkcnt,
void *dst);
return mmc_bread(0, start512, blocks512, buf);
}
/* return nonzero if we believe we run on GTA02 */
int is_this_board_gta02(void)
{
/* look for GTA02 NOR */
*(volatile unsigned short *)(0x18000000) = 0x98;
return !!(*(volatile unsigned short *)(0x18000000) == 0x0020);
}
const struct board_variant const * get_board_variant_gta02(void)
{
return &board_variants[gta02_get_pcb_revision() & 1];
}
static void putc_gta02(char c)
{
serial_putc_s3c24xx(GTA02_DEBUG_UART, c);
}
static void close_gta02(void)
{
/* explicitly clear any pending 8s timeout */
i2c_write_sync(&bb_s3c24xx, PCF50633_I2C_ADS, PCF50633_REG_OOCSHDWN, 0x04);
/* clear any pending timeouts by reading interrupts */
i2c_read_sync(&bb_s3c24xx, PCF50633_I2C_ADS, PCF50633_REG_INT1);
i2c_read_sync(&bb_s3c24xx, PCF50633_I2C_ADS, PCF50633_REG_INT2);
i2c_read_sync(&bb_s3c24xx, PCF50633_I2C_ADS, PCF50633_REG_INT3);
i2c_read_sync(&bb_s3c24xx, PCF50633_I2C_ADS, PCF50633_REG_INT4);
i2c_read_sync(&bb_s3c24xx, PCF50633_I2C_ADS, PCF50633_REG_INT5);
/* set I2C GPIO back to peripheral unit */
(bb_s3c24xx.close)();
}
/*
* our API for bootloader on this machine
*/
const struct board_api board_api_gta02 = {
.name = "Freerunner / GTA02",
.linux_machine_id = 1304,
.linux_mem_start = 0x30000000,
.linux_mem_size = (128 * 1024 * 1024),
.linux_tag_placement = 0x30000000 + 0x100,
.get_board_variant = get_board_variant_gta02,
.is_this_board = is_this_board_gta02,
.port_init = port_init_gta02,
.putc = putc_gta02,
.close = close_gta02,
/* these are the ways we could boot GTA02 in order to try */
.kernel_source = {
[0] = {
.name = "SD Card EXT2 Kernel",
.block_init = sd_card_init_gta02,
.block_read = sd_card_block_read_gta02,
.partition_index = 1,
.filesystem = FS_EXT2,
.filepath = "boot/uImage.bin",
.commandline = "mtdparts=physmap-flash:-(nor);" \
"neo1973-nand:" \
"0x00040000(qi)," \
"0x00040000(cmdline)," \
"0x00800000(backupkernel)," \
"0x000a0000(extra)," \
"0x00040000(identity)," \
"0x0f6a0000(backuprootfs) " \
"rootfstype=ext3 " \
"root=/dev/mmcblk0p1 " \
"console=ttySAC2,115200 " \
"loglevel=8 " \
"init=/sbin/init "\
"ro"
},
[1] = {
.name = "NAND Kernel",
.block_read = nand_read_ll,
.offset_blocks512_if_no_partition = 0x80000 / 512,
.filesystem = FS_RAW,
.commandline = "mtdparts=physmap-flash:-(nor);" \
"neo1973-nand:" \
"0x00040000(qi)," \
"0x00040000(cmdline)," \
"0x00800000(backupkernel)," \
"0x000a0000(extra)," \
"0x00040000(identity)," \
"0x0f6a0000(backuprootfs) " \
"rootfstype=jffs2 " \
"root=/dev/mtdblock6 " \
"console=ttySAC2,115200 " \
"loglevel=8 " \
"init=/sbin/init "\
"ro"
},
},
};

289
qiboot/src/gta03/gta03.c
View File

@ -1,289 +0,0 @@
#include <qi.h>
#include <neo_gta03.h>
#include <serial-s3c24xx.h>
#include <ports-s3c24xx.h>
#include <i2c-bitbang-s3c24xx.h>
#include <pcf50633.h>
#include <s3c24xx-mci.h>
#define GTA03_DEBUG_UART 2
#define PCF50633_I2C_ADS 0x73
static const struct board_variant board_variants[] = {
[0] = {
.name = "EVB PCB",
.machine_revision = 0x010,
},
};
void port_init_gta03(void)
{
unsigned int * MPLLCON = (unsigned int *)0x4c000004;
unsigned int * UPLLCON = (unsigned int *)0x4c000008;
unsigned int * CLKDIVN = (unsigned int *)0x4c000014;
//CAUTION:Follow the configuration order for setting the ports.
// 1) setting value(GPnDAT)
// 2) setting control register (GPnCON)
// 3) configure pull-up resistor(GPnUP)
/* 32bit data bus configuration */
/*
* === PORT A GROUP
* Ports : GPA22 GPA21 GPA20 GPA19 GPA18 GPA17 GPA16 GPA15 GPA14 GPA13 GPA12
* Signal : nFCE nRSTOUT nFRE nFWE ALE CLE nGCS5 nGCS4 nGCS3 nGCS2 nGCS1
* Binary : 1 1 1 , 1 1 1 1 , 1 1 1 1
* Ports : GPA11 GPA10 GPA9 GPA8 GPA7 GPA6 GPA5 GPA4 GPA3 GPA2 GPA1 GPA0
* Signal : ADDR26 ADDR25 ADDR24 ADDR23 ADDR22 ADDR21 ADDR20 ADDR19 ADDR18 ADDR17 ADDR16 ADDR0
* Binary : 1 1 1 1 , 1 1 1 1 , 1 1 1 1
*/
rGPACON = 0x007F8FFF;
/*
* ===* PORT B GROUP
* Ports : GPB10 GPB9 GPB8 GPB7 GPB6 GPB5 GPB4 GPB3 GPB2 GPB1 GPB0
* Signal : nXDREQ0 nXDACK0 nXDREQ1 nXDACK1 nSS_KBD nDIS_OFF L3CLOCK L3DATA L3MODE nIrDATXDEN Keyboard
* Setting: INPUT OUTPUT INPUT OUTPUT INPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT
* Binary : 00 , 01 00 , 01 00 , 01 01 , 01 01 , 01 01
*/
rGPBCON = 0x00145554;
rGPBDAT |= (1 <<9 ); /* USB_PULLUP */
rGPBUP = 0x000007FF;
/*
* === PORT C GROUP
* Ports : GPC15 GPC14 GPC13 GPC12 GPC11 GPC10 GPC9 GPC8 GPC7 GPC6 GPC5 GPC4 GPC3 GPC2 GPC1 GPC0
* Signal : VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 LCDVF2 LCDVF1 LCDVF0 VM VFRAME VLINE VCLK LEND
* Binary : 10 10 , 10 10 , 10 10 , 10 10 , 10 10 , 10 10 , 10 10 , 10 10
*/
rGPCCON = 0xAAA776E9;
rGPCUP = 0x0000FFFF;
rGPCDAT |= (1 << 9); /* WLAN_nRESET pull high */
/*
* === PORT D GROUP
* Ports : GPD15 GPD14 GPD13 GPD12 GPD11 GPD10 GPD9 GPD8 GPD7 GPD6 GPD5 GPD4 GPD3 GPD2 GPD1 GPD0
* Signal : VD23 VD22 VD21 VD20 VD19 VD18 VD17 VD16 VD15 VD14 VD13 VD12 VD11 VD10 VD9 VD8
* Binary : 10 10 , 10 10 , 10 10 , 10 10 , 10 10 , 10 10 , 10 10 ,10 10
*/
rGPDCON = 0xAAA0AAA5;
rGPDUP = 0x0000FFFF;
/*
* === PORT E GROUP
* Ports : GPE15 GPE14 GPE13 GPE12 GPE11 GPE10 GPE9 GPE8 GPE7 GPE6 GPE5 GPE4
* Signal : IICSDA IICSCL SPICLK SPIMOSI SPIMISO SDDATA3 SDDATA2 SDDATA1 SDDATA0 SDCMD SDCLK I2SSDO
* Binary : 10 10 , 10 10 , 10 10 , 10 10 , 10 10 , 10 10 ,
* -------------------------------------------------------------------------------------------------------
* Ports : GPE3 GPE2 GPE1 GPE0
* Signal : I2SSDI CDCLK I2SSCLK I2SLRCK
* Binary : 10 10 , 10 10
*/
rGPECON = 0xAAAAAAAA;
rGPEUP = 0x0000FFFF;
/*
* === PORT F GROUP
* Ports : GPF7 GPF6 GPF5 GPF4 GPF3 GPF2 GPF1 GPF0
* Signal : nLED_8 nLED_4 nLED_2 nLED_1 nIRQ_PCMCIA EINT2 KBDINT EINT0
* Setting: Output Output Output Output EINT3 EINT2 EINT1 EINT0
* Binary : 01 01 , 01 01 , 10 10 , 10 10
*/
rGPFCON = 0x0000AAAA;
rGPFUP = 0x000000FF;
/*
* === PORT G GROUP
* Ports : GPG15 GPG14 GPG13 GPG12 GPG11 GPG10 GPG9 GPG8 GPG7 GPG6
* Signal : nYPON YMON nXPON XMON EINT19 DMAMODE1 DMAMODE0 DMASTART KBDSPICLK KBDSPIMOSI
* Setting: nYPON YMON nXPON XMON EINT19 Output Output Output SPICLK1 SPIMOSI1
* Binary : 11 11 , 11 11 , 10 01 , 01 01 , 11 11
* -----------------------------------------------------------------------------------------
* Ports : GPG5 GPG4 GPG3 GPG2 GPG1 GPG0
* Signal : KBDSPIMISO LCD_PWREN EINT11 nSS_SPI IRQ_LAN IRQ_PCMCIA
* Setting: SPIMISO1 LCD_PWRDN EINT11 nSS0 EINT9 EINT8
* Binary : 11 11 , 10 11 , 10 10
*/
rGPGCON = 0x02A9FE5A;
rGPGUP = 0x0000FFFF;
/*
* === PORT H GROUP
* Ports : GPH10 GPH9 GPH8 GPH7 GPH6 GPH5 GPH4 GPH3 GPH2 GPH1 GPH0
* Signal : CLKOUT1 CLKOUT0 UCLK RXD2 TXD2 RXD1 TXD1 RXD0 TXD0 nRTS0 nCTS0
* Binary : 10 , 10 10 , 11 11 , 10 10 , 10 10 , 10 10
*/
/* pulldown on GPH08: UEXTCLK, just floats!
* pulldown GPH0 -- nCTS0 / RTS_MODEM -- floats when GSM off
* pulldown GPH3 -- RXD[0] / TX_MODEM -- floats when GSM off
*/
rGPHCON = 0x0019A0AA;
rGPHUP = 0x000007FF;
/* pulldown on GPJ00: input, just floats! */
/* pulldown on GPJ07: WLAN module WLAN_GPIO0, no ext pull */
rGPJCON = 0x02AAAAAA;
rGPJUP = 0x1FFFF;
/*
* We have to talk to the PMU a little bit
*/
/* We need SD Card rail (HCLDO) at 3.0V */
i2c_write_sync(&bb_s3c24xx, PCF50633_I2C_ADS, PCF50633_REG_HCLDOOUT,
21);
/* switch HCLDO on */
i2c_write_sync(&bb_s3c24xx, PCF50633_I2C_ADS, PCF50633_REG_HCLDOENA, 1);
/* push DOWN1 (CPU Core rail) to 1.7V, allowing 533MHz */
i2c_write_sync(&bb_s3c24xx, PCF50633_I2C_ADS, PCF50633_REG_DOWN1OUT,
0x2b);
/* change CPU clocking to 533MHz 1:4:8 */
/* clock divide 1:4:8 - do it first */
*CLKDIVN = 5;
/* configure UPLL */
*UPLLCON = ((88 << 12) + (4 << 4) + 2);
/* Magic delay: Page 7-19, seven nops between UPLL and MPLL */
asm __volatile__ (
"nop\n"\
"nop\n"\
"nop\n"\
"nop\n"\
"nop\n"\
"nop\n"\
"nop\n"\
);
/* configure MPLL */
*MPLLCON = ((169 << 12) + (2 << 4) + 1);
serial_init_115200_s3c24xx(GTA03_DEBUG_UART, 66 /*MHz PCLK */);
}
/**
* returns PCB revision information in b0, d8, d9
* GTA03 EVB returns 0x000
* GTA03 returns 0x001
*/
int gta03_get_pcb_revision(void)
{
int n;
u32 u;
/* make B0 inputs */
rGPBCON &= ~0x00000003;
/* D8 and D9 inputs */
rGPDCON &= ~0x000f0000;
/* delay after changing pulldowns */
u = rGPBDAT;
u = rGPDDAT;
/* read the version info */
u = rGPBDAT;
n = (u >> (0 - 0))& 0x001;
u = rGPDDAT;
n |= (u >> (8 -1)) & 0x002;
n |= (u >> (9 - 2)) & 0x004;
/*
* when not being interrogated, all of the revision GPIO
* are set to output
*/
/* make B0 high ouput */
rGPBCON |= 0x00000001;
/* D8 and D9 high ouputs */
rGPDCON |= 0x00050000;
return n;
}
const struct board_variant const * get_board_variant_gta03(void)
{
return &board_variants[gta03_get_pcb_revision()];
}
int is_this_board_gta03(void)
{
/* FIXME: find something gta03 specific */
return 1;
}
static void putc_gta03(char c)
{
serial_putc_s3c24xx(GTA03_DEBUG_UART, c);
}
int sd_card_init_gta03(void)
{
return s3c24xx_mmc_init(1);
}
int sd_card_block_read_gta03(unsigned char * buf, unsigned long start512,
int blocks512)
{
return s3c24xx_mmc_bread(0, start512, blocks512, buf);
}
/*
* our API for bootloader on this machine
*/
const struct board_api board_api_gta03 = {
.name = "GTA03-2442",
.linux_machine_id = 1866,
.linux_mem_start = 0x30000000,
.linux_mem_size = (128 * 1024 * 1024),
.linux_tag_placement = 0x30000000 + 0x100,
.get_board_variant = get_board_variant_gta03,
.is_this_board = is_this_board_gta03,
.port_init = port_init_gta03,
.putc = putc_gta03,
/* these are the ways we could boot GTA03 in order to try */
.kernel_source = {
[0] = {
.name = "SD Card EXT2 Kernel",
.block_init = sd_card_init_gta03,
.block_read = sd_card_block_read_gta03,
.partition_index = 1,
.filesystem = FS_EXT2,
.filepath = "boot/uImage.bin",
.commandline = "mtdparts=physmap-flash:-(nor);" \
"neo1973-nand:" \
"0x00040000(qi)," \
"0x00040000(cmdline)," \
"0x00800000(backupkernel)," \
"0x000a0000(extra)," \
"0x00040000(identity)," \
"0x0f6a0000(backuprootfs) " \
"rootfstype=ext2 " \
"root=/dev/mmcblk0p1 " \
"console=ttySAC2,115200 " \
"loglevel=4 " \
"init=/sbin/init "\
"ro"
},
[1] = {
.name = "NAND Kernel",
.block_read = nand_read_ll,
.offset_blocks512_if_no_partition = 0x80000 / 512,
.filesystem = FS_RAW,
.commandline = "mtdparts=neo1973-nand:" \
"0x00040000(qi)," \
"0x00040000(cmdline)," \
"0x00800000(backupkernel)," \
"0x000a0000(extra)," \
"0x00040000(identity)," \
"0x0f6a0000(backuprootfs) " \
"rootfstype=jffs2 " \
"root=/dev/mtdblock6 " \
"console=ttySAC2,115200 " \
"loglevel=4 " \
"init=/sbin/init "\
"ro"
},
},
};

17
qiboot/src/phase2.c
View File

@ -39,13 +39,17 @@ unsigned long partition_length_blocks = 0;
struct kernel_source const * this_kernel = 0; struct kernel_source const * this_kernel = 0;
int raise(int n)
{
return 0;
}
void bootloader_second_phase(void) void bootloader_second_phase(void)
{ {
void (*the_kernel)(int zero, int arch, uint params); void (*the_kernel)(int zero, int arch, uint params);
int kernel = 0; int kernel = 0;
const struct board_variant * board_variant = const struct board_variant * board_variant;
(this_board->get_board_variant)();
/* okay, do the critical port and serial init for our board */ /* okay, do the critical port and serial init for our board */
@ -53,7 +57,8 @@ void bootloader_second_phase(void)
/* stick some hello messages on debug console */ /* stick some hello messages on debug console */
puts("\n\n\nQi Bootloader "stringify2(BUILD_HOST)" " puts("\n\n\nQi Bootloader "stringify2(QI_CPU)" "
stringify2(BUILD_HOST)" "
stringify2(BUILD_VERSION)" " stringify2(BUILD_VERSION)" "
stringify2(BUILD_DATE)"\n"); stringify2(BUILD_DATE)"\n");
@ -145,6 +150,7 @@ void bootloader_second_phase(void)
switch (this_kernel->filesystem) { switch (this_kernel->filesystem) {
case FS_EXT2: case FS_EXT2:
#if 0
if (!ext2fs_mount()) { if (!ext2fs_mount()) {
puts("Unable to mount ext2 filesystem\n"); puts("Unable to mount ext2 filesystem\n");
this_kernel = &this_board-> this_kernel = &this_board->
@ -162,6 +168,7 @@ void bootloader_second_phase(void)
} }
ext2fs_read(kernel_dram, 4096); ext2fs_read(kernel_dram, 4096);
break; break;
#endif
case FS_FAT: case FS_FAT:
/* FIXME */ /* FIXME */
case FS_RAW: case FS_RAW:
@ -199,9 +206,11 @@ void bootloader_second_phase(void)
switch (this_kernel->filesystem) { switch (this_kernel->filesystem) {
case FS_EXT2: case FS_EXT2:
#if 0
/* This read API always restarts from beginning */ /* This read API always restarts from beginning */
ext2fs_read(kernel_dram, kernel_size); ext2fs_read(kernel_dram, kernel_size);
break; break;
#endif
case FS_FAT: case FS_FAT:
/* FIXME */ /* FIXME */
case FS_RAW: case FS_RAW:
@ -297,5 +306,5 @@ void bootloader_second_phase(void)
puts("No usable kernel image found, we've had it :-(\n"); puts("No usable kernel image found, we've had it :-(\n");
while (1) while (1)
blue_on(1); ;
} }

32
qiboot/src/utils.c
View File

@ -26,10 +26,6 @@
static u8 malloc_pool[100 * 1024]; static u8 malloc_pool[100 * 1024];
void * malloc_pointer = &malloc_pool[0]; void * malloc_pointer = &malloc_pool[0];
int raise(int n)
{
return 0;
}
size_t strlen(const char *s) size_t strlen(const char *s)
{ {
@ -139,22 +135,38 @@ void hexdump(unsigned char *start, int len)
void printdec(int n) void printdec(int n)
{ {
int d = 1 * 1000 * 1000 * 1000; int d[] = {
1 * 1000 * 1000 * 1000,
100 * 1000 * 1000,
10 * 1000 * 1000,
1 * 1000 * 1000,
100 * 1000,
10 * 1000,
1 * 1000,
100,
10,
1,
0
};
int flag = 0; int flag = 0;
int div = 0;
if (n < 0) { if (n < 0) {
this_board->putc('-'); this_board->putc('-');
n = -n; n = -n;
} }
while (d) { while (d[div]) {
int r = n / d; int r = 0;
if (r || flag || (d == 1)) { while (n >= d[div]) {
r++;
n -= d[div];
}
if (r || flag || (d[div] == 1)) {
this_board->putc('0' + r); this_board->putc('0' + r);
flag = 1; flag = 1;
} }
n -= r * d; div++;
d = d / 10;
} }
} }