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add jz4750 code
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c7346db1b6
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227
flash-tool/device_stage1/board_4750.c
Executable file
227
flash-tool/device_stage1/board_4750.c
Executable file
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/*
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* Board init routines.
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*
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* (C) Copyright 2009
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* Author: Xiangfu Liu <xiangfu.z@gmail.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 3 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor,
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* Boston, MA 02110-1301, USA
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*/
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#include "jz4750.h"
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#include "configs.h"
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void gpio_init_4750(void)
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{
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__gpio_as_sdram_32bit();
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__gpio_as_uart1();
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__gpio_as_uart0();
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__gpio_as_uart2();
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__gpio_as_uart3();
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__gpio_as_nand_8bit();
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}
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void ccpll_init_4750(void)
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{
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register unsigned int cfcr, plcr1;
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int n2FR[33] = {
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0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
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7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
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9
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};
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// int div[5] = {1, 4, 4, 4, 4}; /* divisors of I:S:P:L:M */
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int nf, pllout2;
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cfcr = ~CPM_CPCCR_ECS &
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(n2FR[1] << CPM_CPCCR_CDIV_BIT) |
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(n2FR[PHM_DIV] << CPM_CPCCR_HDIV_BIT) |
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(n2FR[PHM_DIV] << CPM_CPCCR_PDIV_BIT) |
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(n2FR[PHM_DIV] << CPM_CPCCR_MDIV_BIT) |
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(n2FR[PHM_DIV] << CPM_CPCCR_LDIV_BIT);
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pllout2 = (cfcr & CPM_CPCCR_PCS) ? CFG_CPU_SPEED : (CFG_CPU_SPEED / 2);
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nf = CFG_CPU_SPEED * 2 / CFG_EXTAL;
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plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
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(0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
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(0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
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(0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
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CPM_CPPCR_PLLEN; /* enable PLL */
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/* init PLL */
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REG_CPM_CPCCR = cfcr;
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REG_CPM_CPPCR = plcr1;
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}
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int nf, pllout2;
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void pll_init_4750(void)
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{
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register unsigned int cfcr, plcr1,tmp;
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int n2FR[33] = {
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0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
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7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
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9
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};
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int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:L:M */
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cfcr = CPM_CPCCR_PCS |
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(n2FR[1] << CPM_CPCCR_CDIV_BIT) |
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(n2FR[PHM_DIV] << CPM_CPCCR_HDIV_BIT) |
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(n2FR[PHM_DIV] << CPM_CPCCR_PDIV_BIT) |
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(n2FR[PHM_DIV] << CPM_CPCCR_MDIV_BIT) |
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(n2FR[PHM_DIV] << CPM_CPCCR_LDIV_BIT);
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if (CFG_EXTAL > 16000000)
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cfcr |= CPM_CPCCR_ECS;
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pllout2 = (cfcr & CPM_CPCCR_PCS) ? CFG_CPU_SPEED : (CFG_CPU_SPEED / 2);
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/* Init USB Host clock, pllout2 must be n*48MHz */
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// REG_CPM_UHCCDR = pllout2 / 48000000 - 1;
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nf = CFG_CPU_SPEED * 2 / CFG_EXTAL;
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plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
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(0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
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(0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
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(0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
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CPM_CPPCR_PLLEN; /* enable PLL */
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cfcr |= CPM_CPCCR_UCS; /* set PLL as UDC PHY*/
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tmp = pllout2 / 1000000 / 12 - 1;
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cfcr |= (tmp << CPM_CPCCR_UDIV_BIT); /* set UDC DIV*/
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/* init PLL */
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REG_CPM_CPCCR = cfcr;
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REG_CPM_CPPCR = plcr1;
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}
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void sdram_init_4750(void)
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{
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register unsigned int dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
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register unsigned int sdemode; /*SDRAM Extended Mode*/
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unsigned int cas_latency_sdmr[2] = {
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EMC_SDMR_CAS_2,
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EMC_SDMR_CAS_3,
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};
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unsigned int cas_latency_dmcr[2] = {
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1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */
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2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */
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};
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int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
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cpu_clk = CFG_CPU_SPEED;
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mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
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/* set REG_EMC_DMAR0 for supporting 128MB sdram on DCS0 */
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REG_EMC_DMAR0 = EMC_DMAR0_BASE | EMC_DMAR_MASK_128_128;
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REG_EMC_BCR = 0; /* Disable bus release */
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REG_EMC_RTCSR = 0; /* Disable clock for counting */
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/* Basic DMCR value */
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dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) |
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((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) |
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(SDRAM_BANK4<<EMC_DMCR_BA_BIT) |
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(SDRAM_BW16<<EMC_DMCR_BW_BIT) |
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EMC_DMCR_EPIN |
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cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
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/* SDRAM timimg */
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ns = 1000000000 / mem_clk;
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tmp = SDRAM_TRAS/ns;
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if (tmp < 4) tmp = 4;
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if (tmp > 11) tmp = 11;
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dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT);
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tmp = SDRAM_RCD/ns;
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if (tmp > 3) tmp = 3;
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dmcr |= (tmp << EMC_DMCR_RCD_BIT);
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tmp = SDRAM_TPC/ns;
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if (tmp > 7) tmp = 7;
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dmcr |= (tmp << EMC_DMCR_TPC_BIT);
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tmp = SDRAM_TRWL/ns;
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if (tmp > 3) tmp = 3;
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dmcr |= (tmp << EMC_DMCR_TRWL_BIT);
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tmp = (SDRAM_TRAS + SDRAM_TPC)/ns;
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if (tmp > 14) tmp = 14;
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dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT);
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/* SDRAM mode value */
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sdmode = EMC_SDMR_BT_SEQ |
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EMC_SDMR_OM_NORMAL |
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EMC_SDMR_BL_4 |
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cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
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/* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
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REG_EMC_DMCR = dmcr;
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REG8(EMC_SDMR0|sdmode) = 0;
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if (CONFIG_MOBILE_SDRAM == 1)
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/* Mobile SDRAM Extended Mode Register */
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sdemode = EMC_SDMR_SET_BA1 | EMC_SDMR_DS_FULL | EMC_SDMR_PRSR_ALL;
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/* Wait for precharge, > 200us */
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tmp = (cpu_clk / 1000000) * 1000;
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while (tmp--);
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/* Stage 2. Enable auto-refresh */
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REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH;
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tmp = SDRAM_TREF/ns;
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tmp = tmp/64 + 1;
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if (tmp > 0xff) tmp = 0xff;
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REG_EMC_RTCOR = tmp;
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REG_EMC_RTCNT = 0;
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REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */
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/* Wait for number of auto-refresh cycles */
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tmp = (cpu_clk / 1000000) * 1000;
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while (tmp--);
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/* Stage 3. Mode Register Set */
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REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET | EMC_DMCR_MBSEL_B0;
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REG8(EMC_SDMR0|sdmode) = 0;
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if (CONFIG_MOBILE_SDRAM == 1)
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REG8(EMC_SDMR0|sdemode) = 0; /* Set Mobile SDRAM Extended Mode Register */
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/* Set back to basic DMCR value */
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REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
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/* everything is ok now */
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}
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void serial_setbrg_4750(void)
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{
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volatile u8 *uart_lcr = (volatile u8 *)(UART_BASE + OFF_LCR);
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volatile u8 *uart_dlhr = (volatile u8 *)(UART_BASE + OFF_DLHR);
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volatile u8 *uart_dllr = (volatile u8 *)(UART_BASE + OFF_DLLR);
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u32 baud_div, tmp;
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baud_div = (REG_CPM_CPCCR & CPM_CPCCR_ECS) ?
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(CFG_EXTAL / 32 / CONFIG_BAUDRATE) : (CFG_EXTAL / 16 / CONFIG_BAUDRATE);
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tmp = *uart_lcr;
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tmp |= UART_LCR_DLAB;
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*uart_lcr = tmp;
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*uart_dlhr = (baud_div >> 8) & 0xff;
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*uart_dllr = baud_div & 0xff;
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tmp &= ~UART_LCR_DLAB;
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*uart_lcr = tmp;
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}
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5320
flash-tool/device_stage1/jz4750.h
Executable file
5320
flash-tool/device_stage1/jz4750.h
Executable file
File diff suppressed because it is too large
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