qi-hardware/xburst-tools
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Code

add nand init for u-boot

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This commit is contained in:
Xiangfu Liu 2009-12-06 01:22:31 +08:00
parent 4c8e0f1763
commit 71d4baa6b0
1 changed files with 19 additions and 2 deletions
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21
xbboot/target-stage1/stage1.c
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@ -35,15 +35,17 @@ void gpio_init();
void pll_init(); void pll_init();
void serial_init(); void serial_init();
void sdram_init(); void sdram_init();
void nand_init();
void c_main(void) void c_main(void)
{ {
load_args(); load_args();
gpio_init(); gpio_init();
pll_init();
serial_init(); serial_init();
pll_init();
serial_puts("XBurst boot stage1...\n"); serial_puts("XBurst boot stage1...\n");
sdram_init(); sdram_init();
nand_init();
serial_puts("stage 1 finished: GPIO, clocks, SDRAM, UART setup - now jump back to BOOT ROM...\n"); serial_puts("stage 1 finished: GPIO, clocks, SDRAM, UART setup - now jump back to BOOT ROM...\n");
} }
@ -89,6 +91,8 @@ void gpio_init()
__gpio_as_nand(); __gpio_as_nand();
__gpio_as_sdram_32bit(); __gpio_as_sdram_32bit();
__gpio_as_uart0(); __gpio_as_uart0();
__gpio_as_lcd_18bit();
__gpio_as_msc();
} }
void pll_init() void pll_init()
@ -201,7 +205,14 @@ void sdram_init()
REG_EMC_RTCSR = 0; /* Disable clock for counting */ REG_EMC_RTCSR = 0; /* Disable clock for counting */
/* Fault DMCR value for mode register setting*/ /* Fault DMCR value for mode register setting*/
dmcr0 = (ARG_BUS_WIDTH_16<<EMC_DMCR_BW_BIT) | #define SDRAM_ROW0 11
#define SDRAM_COL0 8
#define SDRAM_BANK40 0
#define SDRAM_BW16 1
dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) |
((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) |
(SDRAM_BANK40<<EMC_DMCR_BA_BIT) |
(SDRAM_BW16<<EMC_DMCR_BW_BIT) |
EMC_DMCR_EPIN | EMC_DMCR_EPIN |
cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)]; cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
@ -269,3 +280,9 @@ void sdram_init()
/* everything is ok now */ /* everything is ok now */
} }
void nand_init()
{
REG_EMC_SMCR1 = 0x094c4400;
REG_EMC_NFCSR |= EMC_NFCSR_NFE1 | EMC_NFCSR_NFCE1; //__nand_enable()
}