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qi-3d7k-regulator-suspend-tune.patch

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Signed-off-by: Andy Green <andy@openmoko.com>
This commit is contained in:
Andy Green 2009-03-07 07:35:25 +00:00 committed by Andy Green
parent e73e47ab93
commit 8858f9a2fc
2 changed files with 11 additions and 7 deletions
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2
qiboot/src/cpu/s3c6410/om_3d7k-steppingstone.c
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@ -87,7 +87,7 @@ const struct board_api board_api_om_3d7k = {
.get_ui_keys = get_ui_keys_om_3d7k, .get_ui_keys = get_ui_keys_om_3d7k,
.commandline_board = "console=tty0 " \ .commandline_board = "console=tty0 " \
"console=ttySAC3,115200 " \ "console=ttySAC3,115200 " \
"init=/bin/sh " \ "init=/sbin/init " \
"loglevel=8 " \ "loglevel=8 " \
"rootdelay=1 no_console_suspend " \ "rootdelay=1 no_console_suspend " \
"ro ", "ro ",

16
qiboot/src/cpu/s3c6410/om_3d7k.c
View File

@ -21,13 +21,17 @@ const struct pcf50633_init om_3d7k_pcf50633_init[] = {
{ PCF50633_REG_AUTOENA, 0x01 }, /* always on */ { PCF50633_REG_AUTOENA, 0x01 }, /* always on */
{ PCF50633_REG_DOWN1OUT, 0x17 }, /* 1.2V (0x17 * .025V + 0.625V) */ { PCF50633_REG_DOWN1OUT, 0x17 }, /* 1.2V (0x17 * .025V + 0.625V) */
/* all of these are down in 3d7k suspend */
{ PCF50633_REG_DOWN1ENA, 0x02 }, /* enabled if GPIO1 = HIGH */ { PCF50633_REG_DOWN1ENA, 0x02 }, /* enabled if GPIO1 = HIGH */
{ PCF50633_REG_LDO1ENA, 0x00 }, /* LCM power on */ { PCF50633_REG_HCLDOENA, 0x02 }, /* Camera 2.8V power off */
{ PCF50633_REG_LDO2ENA, 0x00 }, /* LCM power on */ { PCF50633_REG_LDO1ENA, 0x02 }, /* Gsensor power off */
{ PCF50633_REG_LDO3ENA, 0x01 }, /* Codec power on */ { PCF50633_REG_LDO2ENA, 0x02 }, /* Camera 1.5V power off */
{ PCF50633_REG_LDO4ENA, 0x01 }, /* SD power on */ { PCF50633_REG_LDO3ENA, 0x03 }, /* Codec power ON */
{ PCF50633_REG_LDO5ENA, 0x00 }, /* LCM power on */ { PCF50633_REG_LDO4ENA, 0x03 }, /* SD power ON */
{ PCF50633_REG_LDO6ENA, 0x00 }, /* LCM power on */ { PCF50633_REG_LDO5ENA, 0x02 }, /* BT power off */
{ PCF50633_REG_LDO6ENA, 0x02 }, /* LCM power off */
{ PCF50633_REG_INT1M, 0x00 }, { PCF50633_REG_INT1M, 0x00 },
{ PCF50633_REG_INT2M, 0x00 }, { PCF50633_REG_INT2M, 0x00 },