qi-hardware/xburst-tools
1
0
Fork 0
mirror of git://projects.qi-hardware.com/xburst-tools.git synced 2024-11-26 01:59:44 +02:00
Code

qi-3d7k-additional-power-reg-config.patch

Browse Source 
Signed-off-by: Andy Green <andy@openmoko.com>
This commit is contained in:
Andy Green 2009-03-11 07:32:15 +00:00 committed by Andy Green
parent e8899ba1e1
commit 8b75ed7105
2 changed files with 37 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
qiboot/include/s3c6410.h
View File

@ -174,6 +174,7 @@ typedef enum {
#define NOR_CFG_OFFSET 0x810
#define STOP_CFG_OFFSET 0x814
#define SLEEP_CFG_OFFSET 0x818
#define STOP_MEM_CFG_OFFSET 0x81c
#define OSC_FREQ_OFFSET 0x820
#define OSC_STABLE_OFFSET 0x824
#define PWR_STABLE_OFFSET 0x828
@ -226,7 +227,7 @@ typedef enum {
#define PWR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE+PWR_CFG_OFFSET)
#define EINT_MASK_REG __REG(ELFIN_CLOCK_POWER_BASE+EINT_MASK_OFFSET)
#define NOR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE+NOR_CFG_OFFSET)
#define STOP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE+STOP_CFG_OFFSET)
#define STOP_MEM_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE+STOP_MEM_CFG_OFFSET)
#define SLEEP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE+SLEEP_CFG_OFFSET)
#define OSC_FREQ_REG __REG(ELFIN_CLOCK_POWER_BASE+OSC_FREQ_OFFSET)
#define OSC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE+OSC_CNT_VAL_OFFSET)
@ -276,6 +277,7 @@ typedef enum {
#define NOR_CFG (ELFIN_CLOCK_POWER_BASE+NOR_CFG_OFFSET)
#define STOP_CFG (ELFIN_CLOCK_POWER_BASE+STOP_CFG_OFFSET)
#define SLEEP_CFG (ELFIN_CLOCK_POWER_BASE+SLEEP_CFG_OFFSET)
#define STOP_MEM_CFG (ELFIN_CLOCK_POWER_BASE+STOP_MEM_CFG_OFFSET)
#define OSC_FREQ (ELFIN_CLOCK_POWER_BASE+OSC_FREQ_OFFSET)
#define OSC_CNT_VAL (ELFIN_CLOCK_POWER_BASE+OSC_CNT_VAL_OFFSET)
#define PWR_CNT_VAL (ELFIN_CLOCK_POWER_BASE+PWR_CNT_VAL_OFFSET)

34
qiboot/src/cpu/s3c6410/om_3d7k.c
View File

@ -107,6 +107,39 @@ void port_init_om_3d7k(void)
{
int n;
__REG(PWR_CFG) =
(0 << 17) | /* kill OSCotg clock pad */
(1 << 10) | /* RTC alarm wakeup source */
(0 << 0) /* 27MHz osc off */
;
__REG(STOP_MEM_CFG) =
(0 << 6) | /* modem */
(0 << 5) | /* host IF */
(1 << 4) | /* OTG */
(1 << 3) | /* HSMMC */
(0 << 2) | /* iROM */
(0 << 1) | /* IRDA */
(1 << 0) /* NFCON / steppingstone */
;
__REG(NOR_CFG) =
(1 << 31) | /* reserved */
(0 << 30) | /* iROM */
(0x1fff << 17) | /* reserved */
(1 << 16) | /* ETM domain */
(1 << 15) | /* S domain */
(1 << 14) | /* F domain / LCD */
(0 << 13) | /* P domain / 2D, scaler, TV encoder */
(0 << 12) | /* I domain / JPEG / Camera */
(1 << 11) | /* reserved */
(0 << 10) | /* G domain / 3D */
(0 << 9) | /* V domain / MFC */
(1 << 8) | /* reserved */
(0x00 << 0) /* reserved */
;
__REG(HCLK_GATE) =
(0 << 31) | /* 3D unit */
(1 << 30) | /* reserved */
@ -208,6 +241,7 @@ void port_init_om_3d7k(void)
(1 << 0) /* reserved */
;
/* ---------------------------- Port A ---------------------------- */
__REG(GPACON) =