qi-hardware/xburst-tools
1
0
Fork 0
mirror of git://projects.qi-hardware.com/xburst-tools.git synced 2024-11-26 12:32:50 +02:00
Code

qi-s3c2442-enable-d-cache.patch

Browse Source 
Seems we have no D-Cache enabled before?  Also defeat AUX as EINT

Signed-off-by: Andy Green <andy@openmoko.com>
This commit is contained in:
Andy Green 2008-12-01 01:26:06 +00:00 committed by Andy Green
parent 5c9a2104f9
commit 9a6d9de901
2 changed files with 6 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
qiboot/src/cpu/s3c2442/gta02.c
View File

@ -168,7 +168,7 @@ void port_init_gta02(void)
* Binary : 01 01 , 01 01 , 10 10 , 10 10
*/
/* pulldown on GPF03: TP-4705+debug - debug conn will float */
rGPFCON = 0x0000AAAA;
rGPFCON = 0x00008AAA;
rGPFUP = 0x000000FF & ~(1 << 3);
rGPFDAT = 0x00000000;
@ -366,6 +366,10 @@ static void close_gta02(void)
/* set I2C GPIO back to peripheral unit */
(bb_s3c24xx.close)();
/* aux back to being EINT */
rGPFCON = 0x0000AAAA;
}
static u8 get_ui_keys_gta02(void)

2
qiboot/src/cpu/s3c2442/start.S
View File

@ -298,7 +298,7 @@ cpu_init_crit:
bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
orr r0, r0, #0x00000002 @ set bit 2 (A) Align
orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
orr r0, r0, #0x00005000 @ set bits 14, 12 D and I-Cache
mcr p15, 0, r0, c1, c0, 0
/*