mirror of
git://projects.qi-hardware.com/xburst-tools.git
synced 2025-04-21 12:27:27 +03:00
change the usbboot to ingenic-tools (host side code)
add usb-boot to keep the device code.
This commit is contained in:
xiangfu
30
usb-boot/stage1/Makefile
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30
usb-boot/stage1/Makefile
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@@ -0,0 +1,30 @@
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#
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# Copyright (C) 2006 Ingenic Semiconductor Inc.
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#
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# Makefile for the JZ4740 internal bootrom code.
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#
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CROSS := mipsel-linux-
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CFLAGS := -O2 -mips32 -fno-pic -mno-abicalls
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LDFLAGS := -nostdlib -EL -T target.ld
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OBJS = head.o main.o common.o board_4740.o board_4750.o debug.o
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all: fw.bin
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fw.bin: fw.elf
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$(CROSS)objcopy -O binary $< $@
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$(CROSS)objdump -D $< > fw.dump
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$(CROSS)objdump -h $< > fw.map
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$(CROSS)nm -n $< > System.map
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cp fw.bin ../../../../tools
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fw.elf: $(OBJS)
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$(CROSS)ld $(LDFLAGS) $(OBJS) -o $@
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.c.o:
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$(CROSS)gcc $(CFLAGS) -c $< -o $@
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.S.o:
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$(CROSS)gcc $(CFLAGS) -c $< -o $@
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clean:
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rm -fr *.o *.elf *.bin *.dump *.map
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212
usb-boot/stage1/board_4740.c
Normal file
212
usb-boot/stage1/board_4740.c
Normal file
@@ -0,0 +1,212 @@
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/*
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* board.c
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*
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* Board init routines.
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*
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* Copyright (C) 2006 Ingenic Semiconductor Inc.
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*
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*/
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#include "jz4740.h"
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#include "configs.h"
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void gpio_init_4740(void)
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{
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/*
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* Initialize SDRAM pins
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*/
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#if 0
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/* PORT A: D0 ~ D31 */
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REG_GPIO_PXFUNS(0) = 0xffffffff;
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REG_GPIO_PXSELC(0) = 0xffffffff;
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/* PORT B: A0 ~ A16, DCS#, RAS#, CAS#, CKE#, RDWE#, CKO#, WE0# */
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REG_GPIO_PXFUNS(1) = 0x81f9ffff;
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REG_GPIO_PXSELC(1) = 0x81f9ffff;
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/* PORT C: WE1#, WE2#, WE3# */
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REG_GPIO_PXFUNS(2) = 0x07000000;
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REG_GPIO_PXSELC(2) = 0x07000000;
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/*
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* Initialize Static Memory Pins
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*/
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/* CS4# */
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REG_GPIO_PXFUNS(1) = 0x10000000;
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REG_GPIO_PXSELC(1) = 0x10000000;
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/*
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* Initialize UART0 pins
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*/
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/* PORT D: TXD/RXD */
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REG_GPIO_PXFUNS(3) = 0x06000000;
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REG_GPIO_PXSELS(3) = 0x06000000;
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#endif
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__gpio_as_nand();
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/*
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* Initialize SDRAM pins
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*/
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__gpio_as_sdram_32bit();
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/*
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* Initialize UART0 pins
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*/
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__gpio_as_uart0();
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__gpio_as_uart1();
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}
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void pll_init_4740(void)
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{
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register unsigned int cfcr, plcr1;
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int n2FR[33] = {
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0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
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7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
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9
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};
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// int div[5] = {1, 4, 4, 4, 4}; /* divisors of I:S:P:L:M */
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int nf, pllout2;
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cfcr = CPM_CPCCR_CLKOEN |
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(n2FR[1] << CPM_CPCCR_CDIV_BIT) |
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(n2FR[PHM_DIV] << CPM_CPCCR_HDIV_BIT) |
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(n2FR[PHM_DIV] << CPM_CPCCR_PDIV_BIT) |
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(n2FR[PHM_DIV] << CPM_CPCCR_MDIV_BIT) |
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(n2FR[PHM_DIV] << CPM_CPCCR_LDIV_BIT);
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pllout2 = (cfcr & CPM_CPCCR_PCS) ? CFG_CPU_SPEED : (CFG_CPU_SPEED / 2);
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/* Init UHC clock */
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REG_CPM_UHCCDR = pllout2 / 48000000 - 1;
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nf = CFG_CPU_SPEED * 2 / CFG_EXTAL;
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plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
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(0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
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(0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
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(0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
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CPM_CPPCR_PLLEN; /* enable PLL */
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/* init PLL */
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REG_CPM_CPCCR = cfcr;
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REG_CPM_CPPCR = plcr1;
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}
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void sdram_init_4740(void)
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{
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register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
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unsigned int cas_latency_sdmr[2] = {
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EMC_SDMR_CAS_2,
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EMC_SDMR_CAS_3,
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};
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unsigned int cas_latency_dmcr[2] = {
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1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */
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2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */
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};
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int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
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cpu_clk = CFG_CPU_SPEED;
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mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
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REG_EMC_BCR = 0; /* Disable bus release */
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REG_EMC_RTCSR = 0; /* Disable clock for counting */
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/* Fault DMCR value for mode register setting*/
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#define SDRAM_ROW0 11
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#define SDRAM_COL0 8
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#define SDRAM_BANK40 0
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dmcr0 = ((SDRAM_ROW0-11)<<EMC_DMCR_RA_BIT) |
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((SDRAM_COL0-8)<<EMC_DMCR_CA_BIT) |
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(SDRAM_BANK40<<EMC_DMCR_BA_BIT) |
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(SDRAM_BW16<<EMC_DMCR_BW_BIT) |
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EMC_DMCR_EPIN |
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cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
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/* Basic DMCR value */
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dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) |
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((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) |
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(SDRAM_BANK4<<EMC_DMCR_BA_BIT) |
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(SDRAM_BW16<<EMC_DMCR_BW_BIT) |
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EMC_DMCR_EPIN |
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cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
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/* SDRAM timimg */
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ns = 1000000000 / mem_clk;
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tmp = SDRAM_TRAS/ns;
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if (tmp < 4) tmp = 4;
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if (tmp > 11) tmp = 11;
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dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT);
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tmp = SDRAM_RCD/ns;
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if (tmp > 3) tmp = 3;
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dmcr |= (tmp << EMC_DMCR_RCD_BIT);
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tmp = SDRAM_TPC/ns;
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if (tmp > 7) tmp = 7;
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dmcr |= (tmp << EMC_DMCR_TPC_BIT);
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tmp = SDRAM_TRWL/ns;
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if (tmp > 3) tmp = 3;
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dmcr |= (tmp << EMC_DMCR_TRWL_BIT);
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tmp = (SDRAM_TRAS + SDRAM_TPC)/ns;
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if (tmp > 14) tmp = 14;
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dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT);
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/* SDRAM mode value */
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sdmode = EMC_SDMR_BT_SEQ |
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EMC_SDMR_OM_NORMAL |
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EMC_SDMR_BL_4 |
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cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
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/* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
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REG_EMC_DMCR = dmcr;
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REG8(EMC_SDMR0|sdmode) = 0;
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/* Wait for precharge, > 200us */
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tmp = (cpu_clk / 1000000) * 1000;
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while (tmp--);
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/* Stage 2. Enable auto-refresh */
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REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH;
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tmp = SDRAM_TREF/ns;
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tmp = tmp/64 + 1;
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if (tmp > 0xff) tmp = 0xff;
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REG_EMC_RTCOR = tmp;
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REG_EMC_RTCNT = 0;
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REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */
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/* Wait for number of auto-refresh cycles */
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tmp = (cpu_clk / 1000000) * 1000;
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while (tmp--);
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/* Stage 3. Mode Register Set */
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REG_EMC_DMCR = dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
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REG8(EMC_SDMR0|sdmode) = 0;
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/* Set back to basic DMCR value */
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REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
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/* everything is ok now */
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}
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void serial_setbrg_4740(void)
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{
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volatile u8 *uart_lcr = (volatile u8 *)(UART_BASE + OFF_LCR);
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volatile u8 *uart_dlhr = (volatile u8 *)(UART_BASE + OFF_DLHR);
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volatile u8 *uart_dllr = (volatile u8 *)(UART_BASE + OFF_DLLR);
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u32 baud_div, tmp;
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baud_div = CFG_EXTAL / 16 / CONFIG_BAUDRATE;
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tmp = *uart_lcr;
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tmp |= UART_LCR_DLAB;
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*uart_lcr = tmp;
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*uart_dlhr = (baud_div >> 8) & 0xff;
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*uart_dllr = baud_div & 0xff;
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tmp &= ~UART_LCR_DLAB;
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*uart_lcr = tmp;
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}
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215
usb-boot/stage1/board_4750.c
Normal file
215
usb-boot/stage1/board_4750.c
Normal file
@@ -0,0 +1,215 @@
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/*
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* board.c
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*
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* Board init routines.
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*
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* Copyright (C) 2006 Ingenic Semiconductor Inc.
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*
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*/
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#include "jz4750.h"
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#include "configs.h"
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void gpio_init_4750(void)
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{
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__gpio_as_sdram_32bit();
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__gpio_as_uart1();
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__gpio_as_uart0();
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__gpio_as_uart2();
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__gpio_as_uart3();
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__gpio_as_nand_8bit();
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}
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void ccpll_init_4750(void)
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{
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register unsigned int cfcr, plcr1;
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int n2FR[33] = {
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0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
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7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
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9
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};
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// int div[5] = {1, 4, 4, 4, 4}; /* divisors of I:S:P:L:M */
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int nf, pllout2;
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cfcr = ~CPM_CPCCR_ECS &
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(n2FR[1] << CPM_CPCCR_CDIV_BIT) |
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(n2FR[PHM_DIV] << CPM_CPCCR_HDIV_BIT) |
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(n2FR[PHM_DIV] << CPM_CPCCR_PDIV_BIT) |
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(n2FR[PHM_DIV] << CPM_CPCCR_MDIV_BIT) |
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(n2FR[PHM_DIV] << CPM_CPCCR_LDIV_BIT);
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pllout2 = (cfcr & CPM_CPCCR_PCS) ? CFG_CPU_SPEED : (CFG_CPU_SPEED / 2);
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nf = CFG_CPU_SPEED * 2 / CFG_EXTAL;
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plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
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(0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
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(0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
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(0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
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CPM_CPPCR_PLLEN; /* enable PLL */
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/* init PLL */
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REG_CPM_CPCCR = cfcr;
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REG_CPM_CPPCR = plcr1;
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}
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int nf, pllout2;
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void pll_init_4750(void)
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{
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register unsigned int cfcr, plcr1,tmp;
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int n2FR[33] = {
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0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
|
||||
7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
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9
|
||||
};
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||||
int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:L:M */
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||||
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||||
cfcr = CPM_CPCCR_PCS |
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(n2FR[1] << CPM_CPCCR_CDIV_BIT) |
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(n2FR[PHM_DIV] << CPM_CPCCR_HDIV_BIT) |
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||||
(n2FR[PHM_DIV] << CPM_CPCCR_PDIV_BIT) |
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||||
(n2FR[PHM_DIV] << CPM_CPCCR_MDIV_BIT) |
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||||
(n2FR[PHM_DIV] << CPM_CPCCR_LDIV_BIT);
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||||
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||||
if (CFG_EXTAL > 16000000)
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||||
cfcr |= CPM_CPCCR_ECS;
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||||
|
||||
pllout2 = (cfcr & CPM_CPCCR_PCS) ? CFG_CPU_SPEED : (CFG_CPU_SPEED / 2);
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||||
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||||
/* Init USB Host clock, pllout2 must be n*48MHz */
|
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// REG_CPM_UHCCDR = pllout2 / 48000000 - 1;
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||||
nf = CFG_CPU_SPEED * 2 / CFG_EXTAL;
|
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plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
|
||||
(0 << CPM_CPPCR_PLLN_BIT) | /* RD=0, NR=2 */
|
||||
(0 << CPM_CPPCR_PLLOD_BIT) | /* OD=0, NO=1 */
|
||||
(0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
|
||||
CPM_CPPCR_PLLEN; /* enable PLL */
|
||||
|
||||
cfcr |= CPM_CPCCR_UCS; /* set PLL as UDC PHY*/
|
||||
tmp = pllout2 / 1000000 / 12 - 1;
|
||||
cfcr |= (tmp << CPM_CPCCR_UDIV_BIT); /* set UDC DIV*/
|
||||
|
||||
/* init PLL */
|
||||
REG_CPM_CPCCR = cfcr;
|
||||
REG_CPM_CPPCR = plcr1;
|
||||
}
|
||||
|
||||
void sdram_init_4750(void)
|
||||
{
|
||||
register unsigned int dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
|
||||
register unsigned int sdemode; /*SDRAM Extended Mode*/
|
||||
|
||||
unsigned int cas_latency_sdmr[2] = {
|
||||
EMC_SDMR_CAS_2,
|
||||
EMC_SDMR_CAS_3,
|
||||
};
|
||||
|
||||
unsigned int cas_latency_dmcr[2] = {
|
||||
1 << EMC_DMCR_TCL_BIT, /* CAS latency is 2 */
|
||||
2 << EMC_DMCR_TCL_BIT /* CAS latency is 3 */
|
||||
};
|
||||
|
||||
int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
|
||||
|
||||
cpu_clk = CFG_CPU_SPEED;
|
||||
mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
|
||||
|
||||
/* set REG_EMC_DMAR0 for supporting 128MB sdram on DCS0 */
|
||||
REG_EMC_DMAR0 = EMC_DMAR0_BASE | EMC_DMAR_MASK_128_128;
|
||||
|
||||
REG_EMC_BCR = 0; /* Disable bus release */
|
||||
REG_EMC_RTCSR = 0; /* Disable clock for counting */
|
||||
|
||||
/* Basic DMCR value */
|
||||
dmcr = ((SDRAM_ROW-11)<<EMC_DMCR_RA_BIT) |
|
||||
((SDRAM_COL-8)<<EMC_DMCR_CA_BIT) |
|
||||
(SDRAM_BANK4<<EMC_DMCR_BA_BIT) |
|
||||
(SDRAM_BW16<<EMC_DMCR_BW_BIT) |
|
||||
EMC_DMCR_EPIN |
|
||||
cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
|
||||
|
||||
/* SDRAM timimg */
|
||||
ns = 1000000000 / mem_clk;
|
||||
tmp = SDRAM_TRAS/ns;
|
||||
if (tmp < 4) tmp = 4;
|
||||
if (tmp > 11) tmp = 11;
|
||||
dmcr |= ((tmp-4) << EMC_DMCR_TRAS_BIT);
|
||||
tmp = SDRAM_RCD/ns;
|
||||
if (tmp > 3) tmp = 3;
|
||||
dmcr |= (tmp << EMC_DMCR_RCD_BIT);
|
||||
tmp = SDRAM_TPC/ns;
|
||||
if (tmp > 7) tmp = 7;
|
||||
dmcr |= (tmp << EMC_DMCR_TPC_BIT);
|
||||
tmp = SDRAM_TRWL/ns;
|
||||
if (tmp > 3) tmp = 3;
|
||||
dmcr |= (tmp << EMC_DMCR_TRWL_BIT);
|
||||
tmp = (SDRAM_TRAS + SDRAM_TPC)/ns;
|
||||
if (tmp > 14) tmp = 14;
|
||||
dmcr |= (((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT);
|
||||
|
||||
/* SDRAM mode value */
|
||||
sdmode = EMC_SDMR_BT_SEQ |
|
||||
EMC_SDMR_OM_NORMAL |
|
||||
EMC_SDMR_BL_4 |
|
||||
cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
|
||||
|
||||
/* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
|
||||
REG_EMC_DMCR = dmcr;
|
||||
REG8(EMC_SDMR0|sdmode) = 0;
|
||||
|
||||
if (CONFIG_MOBILE_SDRAM == 1)
|
||||
/* Mobile SDRAM Extended Mode Register */
|
||||
sdemode = EMC_SDMR_SET_BA1 | EMC_SDMR_DS_FULL | EMC_SDMR_PRSR_ALL;
|
||||
|
||||
/* Wait for precharge, > 200us */
|
||||
tmp = (cpu_clk / 1000000) * 1000;
|
||||
while (tmp--);
|
||||
|
||||
/* Stage 2. Enable auto-refresh */
|
||||
REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH;
|
||||
|
||||
tmp = SDRAM_TREF/ns;
|
||||
tmp = tmp/64 + 1;
|
||||
if (tmp > 0xff) tmp = 0xff;
|
||||
REG_EMC_RTCOR = tmp;
|
||||
REG_EMC_RTCNT = 0;
|
||||
REG_EMC_RTCSR = EMC_RTCSR_CKS_64; /* Divisor is 64, CKO/64 */
|
||||
|
||||
/* Wait for number of auto-refresh cycles */
|
||||
tmp = (cpu_clk / 1000000) * 1000;
|
||||
while (tmp--);
|
||||
|
||||
/* Stage 3. Mode Register Set */
|
||||
REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET | EMC_DMCR_MBSEL_B0;
|
||||
REG8(EMC_SDMR0|sdmode) = 0;
|
||||
|
||||
if (CONFIG_MOBILE_SDRAM == 1)
|
||||
REG8(EMC_SDMR0|sdemode) = 0; /* Set Mobile SDRAM Extended Mode Register */
|
||||
|
||||
/* Set back to basic DMCR value */
|
||||
REG_EMC_DMCR = dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET;
|
||||
|
||||
/* everything is ok now */
|
||||
}
|
||||
|
||||
void serial_setbrg_4750(void)
|
||||
{
|
||||
volatile u8 *uart_lcr = (volatile u8 *)(UART_BASE + OFF_LCR);
|
||||
volatile u8 *uart_dlhr = (volatile u8 *)(UART_BASE + OFF_DLHR);
|
||||
volatile u8 *uart_dllr = (volatile u8 *)(UART_BASE + OFF_DLLR);
|
||||
u32 baud_div, tmp;
|
||||
|
||||
baud_div = (REG_CPM_CPCCR & CPM_CPCCR_ECS) ?
|
||||
(CFG_EXTAL / 32 / CONFIG_BAUDRATE) : (CFG_EXTAL / 16 / CONFIG_BAUDRATE);
|
||||
tmp = *uart_lcr;
|
||||
tmp |= UART_LCR_DLAB;
|
||||
*uart_lcr = tmp;
|
||||
|
||||
*uart_dlhr = (baud_div >> 8) & 0xff;
|
||||
*uart_dllr = baud_div & 0xff;
|
||||
|
||||
tmp &= ~UART_LCR_DLAB;
|
||||
*uart_lcr = tmp;
|
||||
}
|
||||
|
||||
89
usb-boot/stage1/common.c
Normal file
89
usb-boot/stage1/common.c
Normal file
@@ -0,0 +1,89 @@
|
||||
#include "jz4740.h"
|
||||
#include "configs.h"
|
||||
|
||||
void serial_putc (const char c)
|
||||
{
|
||||
volatile u8 *uart_lsr = (volatile u8 *)(UART_BASE + OFF_LSR);
|
||||
volatile u8 *uart_tdr = (volatile u8 *)(UART_BASE + OFF_TDR);
|
||||
|
||||
if (c == '\n') serial_putc ('\r');
|
||||
|
||||
/* Wait for fifo to shift out some bytes */
|
||||
while ( !((*uart_lsr & (UART_LSR_TDRQ | UART_LSR_TEMT)) == 0x60) );
|
||||
|
||||
*uart_tdr = (u8)c;
|
||||
}
|
||||
|
||||
void serial_puts (const char *s)
|
||||
{
|
||||
while (*s) {
|
||||
serial_putc (*s++);
|
||||
}
|
||||
}
|
||||
|
||||
int serial_getc (void)
|
||||
{
|
||||
volatile u8 *uart_rdr = (volatile u8 *)(UART_BASE + OFF_RDR);
|
||||
|
||||
while (!serial_tstc());
|
||||
|
||||
return *uart_rdr;
|
||||
}
|
||||
|
||||
int serial_tstc (void)
|
||||
{
|
||||
volatile u8 *uart_lsr = (volatile u8 *)(UART_BASE + OFF_LSR);
|
||||
|
||||
if (*uart_lsr & UART_LSR_DR) {
|
||||
/* Data in rfifo */
|
||||
return (1);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void serial_init(void)
|
||||
{
|
||||
volatile u8 *uart_fcr = (volatile u8 *)(UART_BASE + OFF_FCR);
|
||||
volatile u8 *uart_lcr = (volatile u8 *)(UART_BASE + OFF_LCR);
|
||||
volatile u8 *uart_ier = (volatile u8 *)(UART_BASE + OFF_IER);
|
||||
volatile u8 *uart_sircr = (volatile u8 *)(UART_BASE + OFF_SIRCR);
|
||||
|
||||
/* Disable port interrupts while changing hardware */
|
||||
*uart_ier = 0;
|
||||
|
||||
/* Disable UART unit function */
|
||||
*uart_fcr = ~UART_FCR_UUE;
|
||||
|
||||
/* Set both receiver and transmitter in UART mode (not SIR) */
|
||||
*uart_sircr = ~(SIRCR_RSIRE | SIRCR_TSIRE);
|
||||
|
||||
/* Set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
|
||||
*uart_lcr = UART_LCR_WLEN_8 | UART_LCR_STOP_1;
|
||||
|
||||
/* Set baud rate */
|
||||
if ( CPU_ID == 0x4740 )
|
||||
serial_setbrg_4740();
|
||||
else
|
||||
serial_setbrg_4750();
|
||||
|
||||
/* Enable UART unit, enable and clear FIFO */
|
||||
*uart_fcr = UART_FCR_UUE | UART_FCR_FE | UART_FCR_TFLS | UART_FCR_RFLS;
|
||||
}
|
||||
|
||||
void serial_put_hex(unsigned int d)
|
||||
{
|
||||
unsigned char c[12];
|
||||
char i;
|
||||
for(i = 0; i < 8;i++)
|
||||
{
|
||||
c[i] = (d >> ((7 - i) * 4)) & 0xf;
|
||||
if(c[i] < 10)
|
||||
c[i] += 0x30;
|
||||
else
|
||||
c[i] += (0x41 - 10);
|
||||
}
|
||||
c[8] = '\n';
|
||||
c[9] = 0;
|
||||
serial_puts(c);
|
||||
|
||||
}
|
||||
67
usb-boot/stage1/configs.h
Normal file
67
usb-boot/stage1/configs.h
Normal file
@@ -0,0 +1,67 @@
|
||||
#ifndef _CONFIGS_H
|
||||
#define _CONFIGS_H
|
||||
|
||||
//Here are these common definitions
|
||||
//Once your system configration change,just modify the file
|
||||
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* SDRAM BANK Number: 1, 2*/
|
||||
#define SDRAM_CASL 3 /* CAS latency: 2 or 3 */
|
||||
// SDRAM Timings, unit: ns
|
||||
#define SDRAM_TRAS 45 /* RAS# Active Time */
|
||||
#define SDRAM_RCD 20 /* RAS# to CAS# Delay */
|
||||
#define SDRAM_TPC 20 /* RAS# Precharge Time */
|
||||
#define SDRAM_TRWL 7 /* Write Latency Time */
|
||||
#define SDRAM_TREF 15625 /* Refresh period: 4096 refresh cycles/64ms */
|
||||
|
||||
extern volatile u32 CPU_ID;
|
||||
extern volatile u8 SDRAM_BW16;
|
||||
extern volatile u8 SDRAM_BANK4;
|
||||
extern volatile u8 SDRAM_ROW;
|
||||
extern volatile u8 SDRAM_COL;
|
||||
extern volatile u8 CONFIG_MOBILE_SDRAM;
|
||||
extern volatile u32 CFG_CPU_SPEED;
|
||||
extern volatile u8 PHM_DIV;
|
||||
extern volatile u32 CFG_EXTAL;
|
||||
extern volatile u32 CONFIG_BAUDRATE;
|
||||
extern volatile u32 UART_BASE;
|
||||
extern volatile u8 CONFIG_MOBILE_SDRAM;
|
||||
extern volatile u8 IS_SHARE;
|
||||
|
||||
typedef struct {
|
||||
/* CPU ID */
|
||||
unsigned int cpu_id;
|
||||
/* PLL args */
|
||||
unsigned char ext_clk;
|
||||
unsigned char cpu_speed;
|
||||
unsigned char phm_div;
|
||||
unsigned char use_uart;
|
||||
unsigned int boudrate;
|
||||
|
||||
/* SDRAM args */
|
||||
unsigned char bus_width;
|
||||
unsigned char bank_num;
|
||||
unsigned char row_addr;
|
||||
unsigned char col_addr;
|
||||
unsigned char is_mobile;
|
||||
unsigned char is_busshare;
|
||||
|
||||
/* debug args */
|
||||
unsigned char debug_ops;
|
||||
unsigned char pin_num;
|
||||
unsigned int start;
|
||||
unsigned int size;
|
||||
}fw_args_t;
|
||||
|
||||
extern void gpio_init_4740(void);
|
||||
extern void sdram_init_4740(void);
|
||||
extern void serial_init_4740(void);
|
||||
extern void pll_init_4740(void);
|
||||
|
||||
extern void gpio_init_4750(void);
|
||||
extern void sdram_init_4750(void);
|
||||
extern void serial_init_4750(void);
|
||||
extern void pll_init_4750(void);
|
||||
|
||||
extern void serial_puts(const char *s);
|
||||
|
||||
#endif
|
||||
81
usb-boot/stage1/debug.c
Normal file
81
usb-boot/stage1/debug.c
Normal file
@@ -0,0 +1,81 @@
|
||||
#include "jz4750.h"
|
||||
#include "configs.h"
|
||||
|
||||
extern fw_args_t * fw_args;
|
||||
|
||||
unsigned int check_sdram(unsigned int saddr, unsigned int size)
|
||||
{
|
||||
unsigned int addr,err = 0;
|
||||
|
||||
serial_puts("\nCheck SDRAM ... \n");
|
||||
saddr += 0xa0000000;
|
||||
size += saddr;
|
||||
serial_put_hex(saddr);
|
||||
serial_put_hex(size);
|
||||
saddr &= 0xfffffffc; //must word align
|
||||
for (addr = saddr; addr < size; addr += 4)
|
||||
{
|
||||
*(volatile unsigned int *)addr = addr;
|
||||
if (*(volatile unsigned int *)addr != addr)
|
||||
{
|
||||
serial_put_hex(addr);
|
||||
err = addr;
|
||||
}
|
||||
}
|
||||
if (err)
|
||||
serial_puts("Check SDRAM fail!\n");
|
||||
else
|
||||
serial_puts("Check SDRAM pass!\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
void gpio_test(unsigned char ops, unsigned char pin)
|
||||
{
|
||||
__gpio_as_output(pin);
|
||||
if (ops)
|
||||
{
|
||||
serial_puts("\nGPIO set ");
|
||||
serial_put_hex(pin);
|
||||
__gpio_set_pin(pin);
|
||||
}
|
||||
else
|
||||
{
|
||||
serial_puts("\nGPIO clear ");
|
||||
serial_put_hex(pin);
|
||||
__gpio_clear_pin(pin);
|
||||
}
|
||||
// __gpio_as_input(pin);
|
||||
}
|
||||
|
||||
void do_debug()
|
||||
{
|
||||
switch (fw_args->debug_ops)
|
||||
{
|
||||
case 1: //sdram check
|
||||
switch (CPU_ID)
|
||||
{
|
||||
case 0x4740:
|
||||
gpio_init_4740();
|
||||
serial_init();
|
||||
sdram_init_4740();
|
||||
break;
|
||||
case 0x4750:
|
||||
gpio_init_4750();
|
||||
serial_init();
|
||||
sdram_init_4750();
|
||||
break;
|
||||
default:;
|
||||
}
|
||||
REG8(USB_REG_INDEX) = 1;
|
||||
REG32(USB_FIFO_EP1) = check_sdram(fw_args->start, fw_args->size);
|
||||
REG32(USB_FIFO_EP1) = 0x0;
|
||||
REG8(USB_REG_INCSR) |= USB_INCSR_INPKTRDY;
|
||||
break;
|
||||
case 2: //set gpio
|
||||
gpio_test(1, fw_args->pin_num);
|
||||
break;
|
||||
case 3: //clear gpio
|
||||
gpio_test(0, fw_args->pin_num);
|
||||
break;
|
||||
}
|
||||
}
|
||||
38
usb-boot/stage1/head.S
Normal file
38
usb-boot/stage1/head.S
Normal file
@@ -0,0 +1,38 @@
|
||||
/*
|
||||
* head.S
|
||||
*
|
||||
* Entry point of the firmware.
|
||||
* The firmware code are executed in the ICache.
|
||||
*
|
||||
* Copyright (C) 2006 Ingenic Semiconductor Inc.
|
||||
*
|
||||
*/
|
||||
|
||||
.text
|
||||
|
||||
.extern c_main
|
||||
|
||||
.globl _start
|
||||
.set noreorder
|
||||
_start:
|
||||
b real_start
|
||||
nop
|
||||
/* reserve 8 words for args */
|
||||
.word 0x0 //it's address is 0x80000008
|
||||
.word 0x0
|
||||
.word 0x0
|
||||
.word 0x0
|
||||
.word 0x0
|
||||
.word 0x0
|
||||
.word 0x0
|
||||
.word 0x0
|
||||
|
||||
real_start:
|
||||
//----------------------------------------------------
|
||||
// setup stack, jump to C code
|
||||
//----------------------------------------------------
|
||||
la $29, 0x80004000 // sp
|
||||
j c_main
|
||||
nop
|
||||
|
||||
.set reorder
|
||||
4859
usb-boot/stage1/jz4740.h
Normal file
4859
usb-boot/stage1/jz4740.h
Normal file
File diff suppressed because it is too large
Load Diff
5302
usb-boot/stage1/jz4750.h
Normal file
5302
usb-boot/stage1/jz4750.h
Normal file
File diff suppressed because it is too large
Load Diff
112
usb-boot/stage1/main.c
Normal file
112
usb-boot/stage1/main.c
Normal file
@@ -0,0 +1,112 @@
|
||||
/*
|
||||
* main.c
|
||||
*
|
||||
* Main routine of the firmware.
|
||||
*
|
||||
* Copyright (C) 2008 Ingenic Semiconductor Inc.
|
||||
*
|
||||
*/
|
||||
#include "jz4740.h"
|
||||
#include "configs.h"
|
||||
|
||||
fw_args_t * fw_args;
|
||||
volatile u32 CPU_ID;
|
||||
volatile u32 UART_BASE;
|
||||
volatile u32 CONFIG_BAUDRATE;
|
||||
volatile u8 SDRAM_BW16;
|
||||
volatile u8 SDRAM_BANK4;
|
||||
volatile u8 SDRAM_ROW;
|
||||
volatile u8 SDRAM_COL;
|
||||
volatile u8 CONFIG_MOBILE_SDRAM;
|
||||
volatile u32 CFG_CPU_SPEED;
|
||||
volatile u32 CFG_EXTAL;
|
||||
volatile u8 PHM_DIV;
|
||||
volatile u8 IS_SHARE;
|
||||
extern int pllout2;
|
||||
#if 0
|
||||
void test_load_args(void)
|
||||
{
|
||||
CPU_ID = 0x4740 ;
|
||||
CFG_EXTAL = 12000000 ;
|
||||
CFG_CPU_SPEED = 336000000 ;
|
||||
PHM_DIV = 4;
|
||||
fw_args->use_uart = 0;
|
||||
UART_BASE = UART0_BASE + fw_args->use_uart * 0x1000;
|
||||
CONFIG_BAUDRATE = 57600;
|
||||
SDRAM_BW16 = 0;
|
||||
SDRAM_BANK4 = 1;
|
||||
SDRAM_ROW = 13;
|
||||
SDRAM_COL = 9;
|
||||
CONFIG_MOBILE_SDRAM = 0;
|
||||
IS_SHARE = 1;
|
||||
}
|
||||
#endif
|
||||
|
||||
void load_args(void)
|
||||
{
|
||||
fw_args = (fw_args_t *)0x80002008; //get the fw args from memory
|
||||
CPU_ID = fw_args->cpu_id ;
|
||||
CFG_EXTAL = (u32)fw_args->ext_clk * 1000000;
|
||||
CFG_CPU_SPEED = (u32)fw_args->cpu_speed * CFG_EXTAL ;
|
||||
if (CFG_EXTAL == 19000000)
|
||||
{
|
||||
CFG_EXTAL = 19200000;
|
||||
CFG_CPU_SPEED = 192000000;
|
||||
}
|
||||
PHM_DIV = fw_args->phm_div;
|
||||
if ( fw_args->use_uart > 3 ) fw_args->use_uart = 0;
|
||||
UART_BASE = UART0_BASE + fw_args->use_uart * 0x1000;
|
||||
CONFIG_BAUDRATE = fw_args->boudrate;
|
||||
SDRAM_BW16 = fw_args->bus_width;
|
||||
SDRAM_BANK4 = fw_args->bank_num;
|
||||
SDRAM_ROW = fw_args->row_addr;
|
||||
SDRAM_COL = fw_args->col_addr;
|
||||
CONFIG_MOBILE_SDRAM = fw_args->is_mobile;
|
||||
IS_SHARE = fw_args->is_busshare;
|
||||
}
|
||||
|
||||
void c_main(void)
|
||||
{
|
||||
load_args();
|
||||
|
||||
if (fw_args->debug_ops > 0)
|
||||
{
|
||||
do_debug();
|
||||
return ;
|
||||
}
|
||||
|
||||
switch (CPU_ID)
|
||||
{
|
||||
case 0x4740:
|
||||
gpio_init_4740();
|
||||
pll_init_4740();
|
||||
serial_init();
|
||||
sdram_init_4740();
|
||||
break;
|
||||
case 0x4750:
|
||||
gpio_init_4750();
|
||||
pll_init_4750();
|
||||
serial_init();
|
||||
sdram_init_4750();
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
#if 1
|
||||
serial_puts("Setup fw args as:\n");
|
||||
serial_put_hex(CPU_ID);
|
||||
serial_put_hex(CFG_EXTAL);
|
||||
serial_put_hex(CFG_CPU_SPEED);
|
||||
serial_put_hex(PHM_DIV);
|
||||
serial_put_hex(fw_args->use_uart);
|
||||
serial_put_hex(CONFIG_BAUDRATE);
|
||||
serial_put_hex(SDRAM_BW16);
|
||||
serial_put_hex(SDRAM_BANK4);
|
||||
serial_put_hex(SDRAM_ROW);
|
||||
serial_put_hex(SDRAM_COL);
|
||||
serial_put_hex(pllout2);
|
||||
serial_put_hex(REG_CPM_CPCCR);
|
||||
serial_puts("Fw run finish !\n");
|
||||
#endif
|
||||
}
|
||||
|
||||
31
usb-boot/stage1/target.ld
Normal file
31
usb-boot/stage1/target.ld
Normal file
@@ -0,0 +1,31 @@
|
||||
OUTPUT_ARCH(mips)
|
||||
ENTRY(_start)
|
||||
MEMORY
|
||||
{
|
||||
ram : ORIGIN = 0x80002000 , LENGTH = 0x100000
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
. = ALIGN(4);
|
||||
.text : { *(.text*) } > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(.rodata*) } > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
.sdata : { *(.sdata*) } > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data*) *(.scommon*) *(.reginfo*) } > ram
|
||||
|
||||
_gp = ABSOLUTE(.); /* Base of small data */
|
||||
|
||||
.got : { *(.got*) } > ram
|
||||
|
||||
. = ALIGN(4);
|
||||
.sbss : { *(.sbss*) } > ram
|
||||
.bss : { *(.bss*) } > ram
|
||||
. = ALIGN (4);
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user