qi-hardware/xburst-tools
1
0
Fork 0
mirror of git://projects.qi-hardware.com/xburst-tools.git synced 2025-04-21 12:27:27 +03:00
Code Activity

qi-add-missed-files-for-scm.patch

Browse Source 
Moved several files and they didn't get added to git

Signed-off-by: Andy Green <andy@openmoko.com>
This commit is contained in:
Andy Green
2008-11-28 10:16:40 +00:00
committed by Andy Green
parent f82d4861e6
commit c3f69eb333
13 changed files with 3783 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

57
qiboot/src/cpu/s3c6410/qi.lds Normal file
View File

@@ -0,0 +1,57 @@
/*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
/* this is intended to take the first 4KBytes of stuff initially.
* We have to make sure we have .rodata* in there for everything
* because we do not compile PIC.
*/
. = ALIGN(4);
.text :
{
src/cpu/s3c6410/start.o (.text .rodata* .data)
src/lowlevel_init.o (.text .rodata* .data)
src/cpu/s3c6410/start_qi.o (.text .rodata* .data)
src/blink_led.o (.text .rodata* .data)
}
. = ALIGN(4);
.everything_else ADDR (.text) + SIZEOF (.text) + 0x53000000 :
AT ( ADDR (.text) + SIZEOF (.text) ) { *(.text .rodata* .data) }
. = 0x53800000 ;
__bss_start = .;
.bss_6410 (NOLOAD) :
{
* (.bss)
}
_end = .;
}

548
qiboot/src/cpu/s3c6410/start.S Normal file
View File

@@ -0,0 +1,548 @@
/*
* (C) Copyright 2007 OpenMoko, Inc.
*
* Configuation settings for the OPENMOKO Neo GTA02 Linux GSM phone
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#define __ASM_MODE__
#define __ASSEMBLY__
#include <s3c6410.h>
#define TEXT_BASE 0x53000000
#define S3C6410_POP_A 0
#define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
/* fixed MPLL 533MHz */
#define MPLL_MDIV 266
#define MPLL_PDIV 3
#define MPLL_SDIV 1
#define Startup_APLLdiv 0
#define APLL_MDIV 266
#define APLL_PDIV 3
#define APLL_SDIV 1
#define Startup_PCLKdiv 3
#define Startup_HCLKdiv 1
#define Startup_MPLLdiv 1
#define Startup_HCLKx2div 1
#define Startup_APLL (12000000/(APLL_PDIV<<APLL_SDIV)*APLL_MDIV)
#define Startup_HCLK (Startup_APLL/(Startup_HCLKx2div+1)/(Startup_HCLKdiv+1))
#define CLK_DIV_VAL ((Startup_PCLKdiv<<12)|(Startup_HCLKx2div<<9)|(Startup_HCLKdiv<<8)|(Startup_MPLLdiv<<4)|Startup_APLLdiv)
#define APLL_VAL set_pll(APLL_MDIV, APLL_PDIV, APLL_SDIV)
#define MPLL_VAL set_pll(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
#if S3C6410_POP_A
#define DMC1_MEM_CFG 0x00210011 /* Supports one CKE control, Chip1, Burst4, Row/Column bit */
#define DMC1_MEM_CFG2 0xB41
#define DMC1_CHIP0_CFG 0x150FC
#define DMC1_CHIP1_CFG 0x154FC
#define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */
/* Memory Parameters */
/* DDR Parameters */
#define DDR_tREFRESH 5865 /* ns */
#define DDR_tRAS 50 /* ns (min: 45ns)*/
#define DDR_tRC 68 /* ns (min: 67.5ns)*/
#define DDR_tRCD 23 /* ns (min: 22.5ns)*/
#define DDR_tRFC 133 /* ns (min: 80ns)*/
#define DDR_tRP 23 /* ns (min: 22.5ns)*/
#define DDR_tRRD 20 /* ns (min: 15ns)*/
#define DDR_tWR 20 /* ns (min: 15ns)*/
#define DDR_tXSR 125 /* ns (min: 120ns)*/
#define DDR_CASL 3 /* CAS Latency 3 */
#else
#define DMC1_MEM_CFG 0x00010012 /* Supports one CKE control, Chip1, Burst4, Row/Column bit */
#define DMC1_MEM_CFG2 0xB45
#define DMC1_CHIP0_CFG 0x150F8
#define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */
/* Memory Parameters */
/* DDR Parameters */
#define DDR_tREFRESH 7800 /* ns */
#define DDR_tRAS 45 /* ns (min: 45ns)*/
#define DDR_tRC 68 /* ns (min: 67.5ns)*/
#define DDR_tRCD 23 /* ns (min: 22.5ns)*/
#define DDR_tRFC 80 /* ns (min: 80ns)*/
#define DDR_tRP 23 /* ns (min: 22.5ns)*/
#define DDR_tRRD 15 /* ns (min: 15ns)*/
#define DDR_tWR 15 /* ns (min: 15ns)*/
#define DDR_tXSR 120 /* ns (min: 120ns)*/
#define DDR_CASL 3 /* CAS Latency 3 */
#endif
/*
* mDDR memory configuration
*/
#define DMC_DDR_BA_EMRS 2
#define DMC_DDR_MEM_CASLAT 3
#define DMC_DDR_CAS_LATENCY (DDR_CASL<<1) //6 Set Cas Latency to 3
#define DMC_DDR_t_DQSS 1 // Min 0.75 ~ 1.25
#define DMC_DDR_t_MRD 2 //Min 2 tck
#define DMC_DDR_t_RAS (((Startup_HCLK / 1000 * DDR_tRAS) - 1) / 1000000 + 1) //7, Min 45ns
#define DMC_DDR_t_RC (((Startup_HCLK / 1000 * DDR_tRC) - 1) / 1000000 + 1) //10, Min 67.5ns
#define DMC_DDR_t_RCD (((Startup_HCLK / 1000 * DDR_tRCD) - 1) / 1000000 + 1) //4,5(TRM), Min 22.5ns
#define DMC_DDR_schedule_RCD ((DMC_DDR_t_RCD - 3) << 3)
#define DMC_DDR_t_RFC (((Startup_HCLK / 1000 * DDR_tRFC) - 1) / 1000000 + 1) //11,18(TRM) Min 80ns
#define DMC_DDR_schedule_RFC ((DMC_DDR_t_RFC - 3) << 5)
#define DMC_DDR_t_RP (((Startup_HCLK / 1000 * DDR_tRP) - 1) / 1000000 + 1) //4, 5(TRM) Min 22.5ns
#define DMC_DDR_schedule_RP ((DMC_DDR_t_RP - 3) << 3)
#define DMC_DDR_t_RRD (((Startup_HCLK / 1000 * DDR_tRRD) - 1) / 1000000 + 1) //3, Min 15ns
#define DMC_DDR_t_WR (((Startup_HCLK / 1000 * DDR_tWR) - 1) / 1000000 + 1) //Min 15ns
#define DMC_DDR_t_WTR 2
#define DMC_DDR_t_XP 2 //1tck + tIS(1.5ns)
#define DMC_DDR_t_XSR (((Startup_HCLK / 1000 * DDR_tXSR) - 1) / 1000000 + 1) //17, Min 120ns
#define DMC_DDR_t_ESR DMC_DDR_t_XSR
#define DMC_DDR_REFRESH_PRD (((Startup_HCLK / 1000 * DDR_tREFRESH) - 1) / 1000000) // TRM 2656
#define DMC_DDR_USER_CONFIG 1 // 2b01 : mDDR
.globl _start, processor_id, is_jtag
_start: b start_code
/* if we are injected by JTAG, the script sets _istag content to nonzero */
is_jtag:
.word 0
/* it's at a fixed address (+0x8) so we can breakpoint it in the JTAG script
* we need to go through this hassle because before this moment, SDRAM is not
* working so we can't prep it from JTAG
*/
_steppingstone_done:
ldr pc, _start_armboot
_start_armboot:
.word start_qi
_TEXT_BASE:
.word TEXT_BASE
processor_id:
.word 0
.word 0x41129200 /* s3c2442 ID */
.word 0x410fb760 /* s3c6410 ID */
/*
* These are defined in the board-specific linker script.
*/
.globl _bss_start
_bss_start:
.word __bss_start
.globl _bss_end
_bss_end:
.word _end
start_code:
/*
* set the cpu to SVC32 mode
*/
mrs r0,cpsr
bic r0,r0,#0x1f
orr r0,r0,#0xd3
msr cpsr,r0
/*
* flush v4 I/D caches
*/
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
/*
* disable MMU stuff and caches
*/
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
orr r0, r0, #0x00000002 @ set bit 2 (A) Align
orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
mcr p15, 0, r0, c1, c0, 0
/* Peri port setup */
ldr r0, =0x70000000
orr r0, r0, #0x13
mcr p15,0,r0,c15,c2,4 @ 256M(0x70000000-0x7fffffff)
ldr r0, =ELFIN_MEM_SYS_CFG @Memory sussystem address 0x7e00f120
mov r1, #0xd @ Xm0CSn2 = NFCON CS0, Xm0CSn3 = NFCON CS1
str r1, [r0]
ldr r0, =ELFIN_DMC1_BASE @DMC1 base address 0x7e001000
ldr r1, =0x04
str r1, [r0, #INDEX_DMC_MEMC_CMD]
ldr r1, =DMC_DDR_REFRESH_PRD
str r1, [r0, #INDEX_DMC_REFRESH_PRD]
ldr r1, =DMC_DDR_CAS_LATENCY
str r1, [r0, #INDEX_DMC_CAS_LATENCY]
ldr r1, =DMC_DDR_t_DQSS
str r1, [r0, #INDEX_DMC_T_DQSS]
ldr r1, =DMC_DDR_t_MRD
str r1, [r0, #INDEX_DMC_T_MRD]
ldr r1, =DMC_DDR_t_RAS
str r1, [r0, #INDEX_DMC_T_RAS]
ldr r1, =DMC_DDR_t_RC
str r1, [r0, #INDEX_DMC_T_RC]
ldr r1, =DMC_DDR_t_RCD
ldr r2, =DMC_DDR_schedule_RCD
orr r1, r1, r2
str r1, [r0, #INDEX_DMC_T_RCD]
ldr r1, =DMC_DDR_t_RFC
ldr r2, =DMC_DDR_schedule_RFC
orr r1, r1, r2
str r1, [r0, #INDEX_DMC_T_RFC]
ldr r1, =DMC_DDR_t_RP
ldr r2, =DMC_DDR_schedule_RP
orr r1, r1, r2
str r1, [r0, #INDEX_DMC_T_RP]
ldr r1, =DMC_DDR_t_RRD
str r1, [r0, #INDEX_DMC_T_RRD]
ldr r1, =DMC_DDR_t_WR
str r1, [r0, #INDEX_DMC_T_WR]
ldr r1, =DMC_DDR_t_WTR
str r1, [r0, #INDEX_DMC_T_WTR]
ldr r1, =DMC_DDR_t_XP
str r1, [r0, #INDEX_DMC_T_XP]
ldr r1, =DMC_DDR_t_XSR
str r1, [r0, #INDEX_DMC_T_XSR]
ldr r1, =DMC_DDR_t_ESR
str r1, [r0, #INDEX_DMC_T_ESR]
ldr r1, =DMC1_MEM_CFG
str r1, [r0, #INDEX_DMC_MEMORY_CFG]
ldr r1, =DMC1_MEM_CFG2
str r1, [r0, #INDEX_DMC_MEMORY_CFG2]
ldr r1, =DMC1_CHIP0_CFG
str r1, [r0, #INDEX_DMC_CHIP_0_CFG]
ldr r1, =DMC_DDR_32_CFG
str r1, [r0, #INDEX_DMC_USER_CONFIG]
@DMC0 DDR Chip 0 configuration direct command reg
ldr r1, =DMC_NOP0
str r1, [r0, #INDEX_DMC_DIRECT_CMD]
@Precharge All
ldr r1, =DMC_PA0
str r1, [r0, #INDEX_DMC_DIRECT_CMD]
@Auto Refresh 2 time
ldr r1, =DMC_AR0
str r1, [r0, #INDEX_DMC_DIRECT_CMD]
str r1, [r0, #INDEX_DMC_DIRECT_CMD]
@MRS
ldr r1, =DMC_mDDR_EMR0
str r1, [r0, #INDEX_DMC_DIRECT_CMD]
@Mode Reg
ldr r1, =DMC_mDDR_MR0
str r1, [r0, #INDEX_DMC_DIRECT_CMD]
#if S3C6410_POP_A
ldr r1, =DMC1_CHIP1_CFG
str r1, [r0, #INDEX_DMC_CHIP_1_CFG]
@DMC0 DDR Chip 0 configuration direct command reg
ldr r1, =DMC_NOP1
str r1, [r0, #INDEX_DMC_DIRECT_CMD]
@Precharge All
ldr r1, =DMC_PA1
str r1, [r0, #INDEX_DMC_DIRECT_CMD]
@Auto Refresh 2 time
ldr r1, =DMC_AR1
str r1, [r0, #INDEX_DMC_DIRECT_CMD]
str r1, [r0, #INDEX_DMC_DIRECT_CMD]
@MRS
ldr r1, =DMC_mDDR_EMR1
str r1, [r0, #INDEX_DMC_DIRECT_CMD]
@Mode Reg
ldr r1, =DMC_mDDR_MR1
str r1, [r0, #INDEX_DMC_DIRECT_CMD]
#endif
@Enable DMC1
mov r1, #0x0
str r1, [r0, #INDEX_DMC_MEMC_CMD]
check_dmc1_ready:
ldr r1, [r0, #INDEX_DMC_MEMC_STATUS]
mov r2, #0x3
and r1, r1, r2
cmp r1, #0x1
bne check_dmc1_ready
nop
ldr r0, =ELFIN_CLOCK_POWER_BASE @0x7e00f000
ldr r1, [r0, #OTHERS_OFFSET]
mov r2, #0x40
orr r1, r1, r2
str r1, [r0, #OTHERS_OFFSET]
nop
nop
nop
nop
nop
ldr r2, =0x80
orr r1, r1, r2
str r1, [r0, #OTHERS_OFFSET]
check_syncack:
ldr r1, [r0, #OTHERS_OFFSET]
ldr r2, =0xf00
and r1, r1, r2
cmp r1, #0xf00
bne check_syncack
mov r1, #0xff00
orr r1, r1, #0xff
str r1, [r0, #APLL_LOCK_OFFSET]
str r1, [r0, #MPLL_LOCK_OFFSET]
str r1, [r0, #EPLL_LOCK_OFFSET]
/* CLKUART(=66.5Mhz) = CLKUART_input(532/2=266Mhz) / (UART_RATIO(3)+1) */
/* CLKUART(=50Mhz) = CLKUART_input(400/2=200Mhz) / (UART_RATIO(3)+1) */
/* Now, When you use UART CLK SRC by EXT_UCLK1, We support 532MHz & 400MHz value */
ldr r1, [r0, #CLK_DIV2_OFFSET]
bic r1, r1, #0x70000
orr r1, r1, #0x30000
str r1, [r0, #CLK_DIV2_OFFSET]
ldr r1, [r0, #CLK_DIV0_OFFSET] /*Set Clock Divider*/
bic r1, r1, #0x30000
bic r1, r1, #0xff00
bic r1, r1, #0xff
ldr r2, =CLK_DIV_VAL
orr r1, r1, r2
str r1, [r0, #CLK_DIV0_OFFSET]
ldr r1, =APLL_VAL
str r1, [r0, #APLL_CON_OFFSET]
ldr r1, =MPLL_VAL
str r1, [r0, #MPLL_CON_OFFSET]
ldr r1, =0x80200203 /* FOUT of EPLL is 96MHz */
str r1, [r0, #EPLL_CON0_OFFSET]
ldr r1, =0x0
str r1, [r0, #EPLL_CON1_OFFSET]
ldr r1, [r0, #CLK_SRC_OFFSET] /* APLL, MPLL, EPLL select to Fout */
ldr r2, =0x2007
orr r1, r1, r2
str r1, [r0, #CLK_SRC_OFFSET]
/* wait at least 200us to stablize all clock */
mov r1, #0x10000
1: subs r1, r1, #1
bne 1b
ldr r1, [r0, #OTHERS_OFFSET]
orr r1, r1, #0x20
str r1, [r0, #OTHERS_OFFSET]
/* set GPIO to enable UART */
@ GPIO setting for UART
ldr r0, =ELFIN_GPIO_BASE
ldr r1, =0x220022
str r1, [r0, #GPACON_OFFSET]
ldr r0, =ELFIN_UART_CONSOLE_BASE @0x7F005000
mov r1, #0x0
str r1, [r0, #UFCON_OFFSET]
str r1, [r0, #UMCON_OFFSET]
mov r1, #0x3 @was 0.
str r1, [r0, #ULCON_OFFSET]
ldr r1, =0xe45 /* UARTCLK SRC = 11 => EXT_UCLK1*/
str r1, [r0, #UCON_OFFSET]
ldr r1, =0x22
str r1, [r0, #UBRDIV_OFFSET]
ldr r1, =0x1FFF
str r1, [r0, #UDIVSLOT_OFFSET]
ldr r1, =0x4f4f4f4f
str r1, [r0, #UTXH_OFFSET] @'O'
/* send out a char to say hello */
ldr r1, =0x55
str r1, [r0, #UTXH_OFFSET]
#if 0
/* Below code is for ARM926EJS and ARM1026EJS */
.globl cleanDCache
cleanDCache:
mrc p15, 0, pc, c7, c10, 3 /* test/clean D-Cache */
bne cleanDCache
mov pc, lr
.globl cleanFlushDCache
cleanFlushDCache:
mrc p15, 0, pc, c7, c14, 3 /* test/cleanflush D-Cache */
bne cleanFlushDCache
mov pc, lr
.globl cleanFlushCache
cleanFlushCache:
mrc p15, 0, pc, c7, c14, 3 /* test/cleanflush D-Cache */
bne cleanFlushCache
mcr p15, 0, r0, c7, c5, 0 /* flush I-Cache */
mov pc, lr
.ltorg
#endif
#if 0
/* enable only CPU peripheral block clocks we actually use */
ldr r0, =0x4c00000c /* clkcon */
ldr r1, =0x3f10 /* uart, pwm, gpio, nand, sdi clocks on */
str r1, [r0]
/* gpio UART2 init, H port */
ldr r0, =0x56000070
ldr r1, =0x001AAAAA
str r1, [r0]
/* enable KEEPACT(GPJ8) to make sure PMU keeps us alive */
ldr r0, =0x56000000 /* GPJ base */
ldr r1, [r0, #0xd0] /* GPJCON */
orr r1, r1, #(1 << 16)
str r1, [r0, #0xd0]
ldr r1, [r0, #0xd4] /* GPJDAT */
orr r1, r1, #(1 << 8)
str r1, [r0, #0xd4]
/* take sdram out of power down */
ldr r0, =0x56000080 /* misccr */
ldr r1, [ r0 ]
bic r1, r1, #(S3C2410_MISCCR_nEN_SCLK0 | S3C2410_MISCCR_nEN_SCLK1 | S3C2410_MISCCR_nEN_SCLKE)
str r1, [ r0 ]
/* ensure signals stabalise */
mov r1, #128
1: subs r1, r1, #1
bpl 1b
bl cpu_init_crit
/* ensure some refresh has happened */
ldr r1, =0xfffff
1: subs r1, r1, #1
bpl 1b
/* capture full EINT situation into gstatus 4 */
ldr r0, =0x4A000000 /* SRCPND */
ldr r1, [ r0 ]
and r1, r1, #0xf
ldr r0, =0x560000BC /* gstatus4 */
str r1, [ r0 ]
ldr r0, =0x560000A8 /* EINTPEND */
ldr r1, [ r0 ]
ldr r0, =0xfff0
and r1, r1, r0
ldr r0, =0x560000BC /* gstatus4 */
ldr r0, [ r0 ]
orr r1, r1, r0
ldr r0, =0x560000BC /* gstatus4 */
str r1, [ r0 ]
/* test for resume */
ldr r1, =0x560000B4 /* gstatus2 */
ldr r0, [ r1 ]
tst r0, #0x02 /* is this resume from power down */
/* well, if it was, we are going to jump to
* whatever address we stashed in gstatus3,
* and gstatus4 will hold the wake interrupt
* source for the OS to look at
*/
ldrne pc, [r1, #4]
#endif
/* >> CFG_VIDEO_LOGO_MAX_SIZE */
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
sub sp, r0, #12 /* leave 3 words for abort-stack */
clear_bss:
ldr r0, _bss_start /* find start of bss segment */
ldr r1, _bss_end /* stop here */
mov r2, #0x00000000 /* clear */
clbss_l:
str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
ble clbss_l
/* we are going to jump into the C part of the init now */
spin:
b _steppingstone_done

105
qiboot/src/cpu/s3c6410/start_qi.c Normal file
View File

@@ -0,0 +1,105 @@
/*
* (C) Copyright 2007 OpenMoko, Inc.
* Author: xiangfu liu <xiangfu@openmoko.org>
* Andy Green <andy@openmoko.com>
*
* Configuation settings for the OPENMOKO Neo GTA02 Linux GSM phone
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* NOTE this stuff runs in steppingstone context! */
#include <qi.h>
#include <neo_tla01.h>
extern void bootloader_second_phase(void);
const struct board_api *boards[] = {
&board_api_tla01,
NULL /* always last */
};
struct board_api const * this_board;
extern int is_jtag;
void start_qi(void)
{
int flag = 0;
int board = 0;
/*
* well, we can be running on this CPU two different ways.
*
* 1) We were copied into steppingstone and TEXT_BASE already
* by JTAG. We don't have to do anything else. JTAG script
* then sets data at address 0x4 to 0xffffffff as a signal we
* are running by JTAG.
*
* 2) We only got our first 4K into steppingstone, we need to copy
* the rest of ourselves into TEXT_BASE.
*
* So we do the copy out of NAND only if we see we did not come up
* under control of JTAG.
*/
if (!is_jtag)
/*
* We got the first 4KBytes of the bootloader pulled into the
* steppingstone SRAM for free. Now we pull the whole bootloader
* image into SDRAM.
*
* This code and the .S files are arranged by the linker script
* to expect to run from 0x0. But the linker script has told
* everything else to expect to run from 0x33000000+. That's
* why we are going to be able to copy this code and not have it
* crash when we run it from there.
*/
/* We randomly pull 32KBytes of bootloader */
/* FIXME this ain't right for s3c6410 */
#if 0
if (nand_read_ll((u8 *)TEXT_BASE, 0, 32 * 1024 / 512) < 0)
goto unhappy;
#endif
/* ask all the boards we support in turn if they recognize this
* hardware we are running on, accept the first positive answer
*/
this_board = boards[board];
while (!flag && this_board) {
/* check if it is the right board... */
if (this_board->is_this_board()) {
flag = 1;
continue;
}
this_board = boards[board++];
}
/*
* jump to bootloader_second_phase() running from DRAM copy
*/
bootloader_second_phase();
#if 0
unhappy:
while(1)
;
#endif
}

246
qiboot/src/cpu/s3c6410/tla01.c Normal file
View File

@@ -0,0 +1,246 @@
#include <qi.h>
#include <neo_tla01.h>
#include <serial-s3c24xx.h>
#include <ports-s3c24xx.h>
#include <i2c-bitbang-s3c24xx.h>
#include <pcf50633.h>
#define GTA03_DEBUG_UART 2
#define PCF50633_I2C_ADS 0x73
static const struct board_variant board_variants[] = {
[0] = {
.name = "TLA01",
.machine_revision = 0x010,
},
};
void port_init_tla01(void)
{
unsigned int * MPLLCON = (unsigned int *)0x4c000004;
unsigned int * UPLLCON = (unsigned int *)0x4c000008;
unsigned int * CLKDIVN = (unsigned int *)0x4c000014;
//CAUTION:Follow the configuration order for setting the ports.
// 1) setting value(GPnDAT)
// 2) setting control register (GPnCON)
// 3) configure pull-up resistor(GPnUP)
/* 32bit data bus configuration */
/*
* === PORT A GROUP
* Ports : GPA22 GPA21 GPA20 GPA19 GPA18 GPA17 GPA16 GPA15 GPA14 GPA13 GPA12
* Signal : nFCE nRSTOUT nFRE nFWE ALE CLE nGCS5 nGCS4 nGCS3 nGCS2 nGCS1
* Binary : 1 1 1 , 1 1 1 1 , 1 1 1 1
* Ports : GPA11 GPA10 GPA9 GPA8 GPA7 GPA6 GPA5 GPA4 GPA3 GPA2 GPA1 GPA0
* Signal : ADDR26 ADDR25 ADDR24 ADDR23 ADDR22 ADDR21 ADDR20 ADDR19 ADDR18 ADDR17 ADDR16 ADDR0
* Binary : 1 1 1 1 , 1 1 1 1 , 1 1 1 1
*/
rGPACON = 0x007F8FFF;
/*
* ===* PORT B GROUP
* Ports : GPB10 GPB9 GPB8 GPB7 GPB6 GPB5 GPB4 GPB3 GPB2 GPB1 GPB0
* Signal : nXDREQ0 nXDACK0 nXDREQ1 nXDACK1 nSS_KBD nDIS_OFF L3CLOCK L3DATA L3MODE nIrDATXDEN Keyboard
* Setting: INPUT OUTPUT INPUT OUTPUT INPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT
* Binary : 00 , 01 00 , 01 00 , 01 01 , 01 01 , 01 01
*/
rGPBCON = 0x00145554;
rGPBDAT |= (1 <<9 ); /* USB_PULLUP */
rGPBUP = 0x000007FF;
/*
* === PORT C GROUP
* Ports : GPC15 GPC14 GPC13 GPC12 GPC11 GPC10 GPC9 GPC8 GPC7 GPC6 GPC5 GPC4 GPC3 GPC2 GPC1 GPC0
* Signal : VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 LCDVF2 LCDVF1 LCDVF0 VM VFRAME VLINE VCLK LEND
* Binary : 10 10 , 10 10 , 10 10 , 10 10 , 10 10 , 10 10 , 10 10 , 10 10
*/
rGPCCON = 0xAAA776E9;
rGPCUP = 0x0000FFFF;
rGPCDAT |= (1 << 9); /* WLAN_nRESET pull high */
/*
* === PORT D GROUP
* Ports : GPD15 GPD14 GPD13 GPD12 GPD11 GPD10 GPD9 GPD8 GPD7 GPD6 GPD5 GPD4 GPD3 GPD2 GPD1 GPD0
* Signal : VD23 VD22 VD21 VD20 VD19 VD18 VD17 VD16 VD15 VD14 VD13 VD12 VD11 VD10 VD9 VD8
* Binary : 10 10 , 10 10 , 10 10 , 10 10 , 10 10 , 10 10 , 10 10 ,10 10
*/
rGPDCON = 0xAAA0AAA5;
rGPDUP = 0x0000FFFF;
/*
* === PORT E GROUP
* Ports : GPE15 GPE14 GPE13 GPE12 GPE11 GPE10 GPE9 GPE8 GPE7 GPE6 GPE5 GPE4
* Signal : IICSDA IICSCL SPICLK SPIMOSI SPIMISO SDDATA3 SDDATA2 SDDATA1 SDDATA0 SDCMD SDCLK I2SSDO
* Binary : 10 10 , 10 10 , 10 10 , 10 10 , 10 10 , 10 10 ,
* -------------------------------------------------------------------------------------------------------
* Ports : GPE3 GPE2 GPE1 GPE0
* Signal : I2SSDI CDCLK I2SSCLK I2SLRCK
* Binary : 10 10 , 10 10
*/
rGPECON = 0xAAAAAAAA;
rGPEUP = 0x0000FFFF;
/*
* === PORT F GROUP
* Ports : GPF7 GPF6 GPF5 GPF4 GPF3 GPF2 GPF1 GPF0
* Signal : nLED_8 nLED_4 nLED_2 nLED_1 nIRQ_PCMCIA EINT2 KBDINT EINT0
* Setting: Output Output Output Output EINT3 EINT2 EINT1 EINT0
* Binary : 01 01 , 01 01 , 10 10 , 10 10
*/
rGPFCON = 0x0000AAAA;
rGPFUP = 0x000000FF;
/*
* === PORT G GROUP
* Ports : GPG15 GPG14 GPG13 GPG12 GPG11 GPG10 GPG9 GPG8 GPG7 GPG6
* Signal : nYPON YMON nXPON XMON EINT19 DMAMODE1 DMAMODE0 DMASTART KBDSPICLK KBDSPIMOSI
* Setting: nYPON YMON nXPON XMON EINT19 Output Output Output SPICLK1 SPIMOSI1
* Binary : 11 11 , 11 11 , 10 01 , 01 01 , 11 11
* -----------------------------------------------------------------------------------------
* Ports : GPG5 GPG4 GPG3 GPG2 GPG1 GPG0
* Signal : KBDSPIMISO LCD_PWREN EINT11 nSS_SPI IRQ_LAN IRQ_PCMCIA
* Setting: SPIMISO1 LCD_PWRDN EINT11 nSS0 EINT9 EINT8
* Binary : 11 11 , 10 11 , 10 10
*/
rGPGCON = 0x02A9FE5A;
rGPGUP = 0x0000FFFF;
/*
* === PORT H GROUP
* Ports : GPH10 GPH9 GPH8 GPH7 GPH6 GPH5 GPH4 GPH3 GPH2 GPH1 GPH0
* Signal : CLKOUT1 CLKOUT0 UCLK RXD2 TXD2 RXD1 TXD1 RXD0 TXD0 nRTS0 nCTS0
* Binary : 10 , 10 10 , 11 11 , 10 10 , 10 10 , 10 10
*/
/* pulldown on GPH08: UEXTCLK, just floats!
* pulldown GPH0 -- nCTS0 / RTS_MODEM -- floats when GSM off
* pulldown GPH3 -- RXD[0] / TX_MODEM -- floats when GSM off
*/
rGPHCON = 0x0019A0AA;
rGPHUP = 0x000007FF;
/* pulldown on GPJ00: input, just floats! */
/* pulldown on GPJ07: WLAN module WLAN_GPIO0, no ext pull */
rGPJCON = 0x02AAAAAA;
rGPJUP = 0x1FFFF;
/*
* We have to talk to the PMU a little bit
*/
/* We need SD Card rail (HCLDO) at 3.0V */
i2c_write_sync(&bb_s3c24xx, PCF50633_I2C_ADS, PCF50633_REG_HCLDOOUT,
21);
/* switch HCLDO on */
i2c_write_sync(&bb_s3c24xx, PCF50633_I2C_ADS, PCF50633_REG_HCLDOENA, 1);
/* push DOWN1 (CPU Core rail) to 1.7V, allowing 533MHz */
i2c_write_sync(&bb_s3c24xx, PCF50633_I2C_ADS, PCF50633_REG_DOWN1OUT,
0x2b);
/* change CPU clocking to 533MHz 1:4:8 */
/* clock divide 1:4:8 - do it first */
*CLKDIVN = 5;
/* configure UPLL */
*UPLLCON = ((88 << 12) + (4 << 4) + 2);
/* Magic delay: Page 7-19, seven nops between UPLL and MPLL */
asm __volatile__ (
"nop\n"\
"nop\n"\
"nop\n"\
"nop\n"\
"nop\n"\
"nop\n"\
"nop\n"\
);
/* configure MPLL */
*MPLLCON = ((169 << 12) + (2 << 4) + 1);
serial_init_115200_s3c24xx(GTA03_DEBUG_UART, 66 /*MHz PCLK */);
}
/**
* returns PCB revision information in b0, d8, d9
* GTA03 EVB returns 0x000
* GTA03 returns 0x001
*/
int tla01_get_pcb_revision(void)
{
int n;
u32 u;
/* make B0 inputs */
rGPBCON &= ~0x00000003;
/* D8 and D9 inputs */
rGPDCON &= ~0x000f0000;
/* delay after changing pulldowns */
u = rGPBDAT;
u = rGPDDAT;
/* read the version info */
u = rGPBDAT;
n = (u >> (0 - 0))& 0x001;
u = rGPDDAT;
n |= (u >> (8 -1)) & 0x002;
n |= (u >> (9 - 2)) & 0x004;
/*
* when not being interrogated, all of the revision GPIO
* are set to output
*/
/* make B0 high ouput */
rGPBCON |= 0x00000001;
/* D8 and D9 high ouputs */
rGPDCON |= 0x00050000;
return n;
}
const struct board_variant const * get_board_variant_tla01(void)
{
return &board_variants[tla01_get_pcb_revision()];
}
int is_this_board_tla01(void)
{
/* FIXME: find something tla01 specific */
return 1;
}
static void putc_tla01(char c)
{
serial_putc_s3c24xx(GTA03_DEBUG_UART, c);
}
/*
* our API for bootloader on this machine
*/
const struct board_api board_api_tla01 = {
.name = "TLA01",
.linux_machine_id = 1866,
.linux_mem_start = 0x30000000,
.linux_mem_size = (128 * 1024 * 1024),
.linux_tag_placement = 0x30000000 + 0x100,
.get_board_variant = get_board_variant_tla01,
.is_this_board = is_this_board_tla01,
.port_init = port_init_tla01,
.putc = putc_tla01,
.kernel_source = {
[0] = {
.name = "SD Card",
.block_read = NULL, /* FIXME It's s3c6400 sd card*/
.offset_blocks512_if_no_partition = 0x80000 / 512,
.filesystem = FS_RAW,
.commandline = "rootfstype=ext3 " \
"root=/dev/mmcblk0p1 " \
"console=ttySAC2,115200 " \
"loglevel=4 " \
"init=/sbin/init "\
"ro"
},
},
};