mirror of
git://projects.qi-hardware.com/xburst-tools.git
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qi-add-missed-files-for-scm.patch
Moved several files and they didn't get added to git Signed-off-by: Andy Green <andy@openmoko.com>
This commit is contained in:
Andy Green
Andy Green
548
qiboot/src/cpu/s3c6410/start.S
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548
qiboot/src/cpu/s3c6410/start.S
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@@ -0,0 +1,548 @@
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/*
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* (C) Copyright 2007 OpenMoko, Inc.
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*
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* Configuation settings for the OPENMOKO Neo GTA02 Linux GSM phone
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#define __ASM_MODE__
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#define __ASSEMBLY__
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#include <s3c6410.h>
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#define TEXT_BASE 0x53000000
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#define S3C6410_POP_A 0
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#define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
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/* fixed MPLL 533MHz */
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#define MPLL_MDIV 266
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#define MPLL_PDIV 3
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#define MPLL_SDIV 1
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#define Startup_APLLdiv 0
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#define APLL_MDIV 266
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#define APLL_PDIV 3
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#define APLL_SDIV 1
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#define Startup_PCLKdiv 3
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#define Startup_HCLKdiv 1
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#define Startup_MPLLdiv 1
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#define Startup_HCLKx2div 1
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#define Startup_APLL (12000000/(APLL_PDIV<<APLL_SDIV)*APLL_MDIV)
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#define Startup_HCLK (Startup_APLL/(Startup_HCLKx2div+1)/(Startup_HCLKdiv+1))
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#define CLK_DIV_VAL ((Startup_PCLKdiv<<12)|(Startup_HCLKx2div<<9)|(Startup_HCLKdiv<<8)|(Startup_MPLLdiv<<4)|Startup_APLLdiv)
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#define APLL_VAL set_pll(APLL_MDIV, APLL_PDIV, APLL_SDIV)
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#define MPLL_VAL set_pll(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
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#if S3C6410_POP_A
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#define DMC1_MEM_CFG 0x00210011 /* Supports one CKE control, Chip1, Burst4, Row/Column bit */
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#define DMC1_MEM_CFG2 0xB41
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#define DMC1_CHIP0_CFG 0x150FC
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#define DMC1_CHIP1_CFG 0x154FC
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#define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */
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/* Memory Parameters */
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/* DDR Parameters */
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#define DDR_tREFRESH 5865 /* ns */
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#define DDR_tRAS 50 /* ns (min: 45ns)*/
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#define DDR_tRC 68 /* ns (min: 67.5ns)*/
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#define DDR_tRCD 23 /* ns (min: 22.5ns)*/
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#define DDR_tRFC 133 /* ns (min: 80ns)*/
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#define DDR_tRP 23 /* ns (min: 22.5ns)*/
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#define DDR_tRRD 20 /* ns (min: 15ns)*/
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#define DDR_tWR 20 /* ns (min: 15ns)*/
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#define DDR_tXSR 125 /* ns (min: 120ns)*/
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#define DDR_CASL 3 /* CAS Latency 3 */
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#else
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#define DMC1_MEM_CFG 0x00010012 /* Supports one CKE control, Chip1, Burst4, Row/Column bit */
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#define DMC1_MEM_CFG2 0xB45
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#define DMC1_CHIP0_CFG 0x150F8
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#define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */
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/* Memory Parameters */
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/* DDR Parameters */
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#define DDR_tREFRESH 7800 /* ns */
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#define DDR_tRAS 45 /* ns (min: 45ns)*/
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#define DDR_tRC 68 /* ns (min: 67.5ns)*/
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#define DDR_tRCD 23 /* ns (min: 22.5ns)*/
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#define DDR_tRFC 80 /* ns (min: 80ns)*/
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#define DDR_tRP 23 /* ns (min: 22.5ns)*/
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#define DDR_tRRD 15 /* ns (min: 15ns)*/
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#define DDR_tWR 15 /* ns (min: 15ns)*/
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#define DDR_tXSR 120 /* ns (min: 120ns)*/
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#define DDR_CASL 3 /* CAS Latency 3 */
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#endif
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/*
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* mDDR memory configuration
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*/
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#define DMC_DDR_BA_EMRS 2
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#define DMC_DDR_MEM_CASLAT 3
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#define DMC_DDR_CAS_LATENCY (DDR_CASL<<1) //6 Set Cas Latency to 3
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#define DMC_DDR_t_DQSS 1 // Min 0.75 ~ 1.25
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#define DMC_DDR_t_MRD 2 //Min 2 tck
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#define DMC_DDR_t_RAS (((Startup_HCLK / 1000 * DDR_tRAS) - 1) / 1000000 + 1) //7, Min 45ns
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#define DMC_DDR_t_RC (((Startup_HCLK / 1000 * DDR_tRC) - 1) / 1000000 + 1) //10, Min 67.5ns
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#define DMC_DDR_t_RCD (((Startup_HCLK / 1000 * DDR_tRCD) - 1) / 1000000 + 1) //4,5(TRM), Min 22.5ns
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#define DMC_DDR_schedule_RCD ((DMC_DDR_t_RCD - 3) << 3)
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#define DMC_DDR_t_RFC (((Startup_HCLK / 1000 * DDR_tRFC) - 1) / 1000000 + 1) //11,18(TRM) Min 80ns
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#define DMC_DDR_schedule_RFC ((DMC_DDR_t_RFC - 3) << 5)
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#define DMC_DDR_t_RP (((Startup_HCLK / 1000 * DDR_tRP) - 1) / 1000000 + 1) //4, 5(TRM) Min 22.5ns
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#define DMC_DDR_schedule_RP ((DMC_DDR_t_RP - 3) << 3)
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#define DMC_DDR_t_RRD (((Startup_HCLK / 1000 * DDR_tRRD) - 1) / 1000000 + 1) //3, Min 15ns
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#define DMC_DDR_t_WR (((Startup_HCLK / 1000 * DDR_tWR) - 1) / 1000000 + 1) //Min 15ns
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#define DMC_DDR_t_WTR 2
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#define DMC_DDR_t_XP 2 //1tck + tIS(1.5ns)
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#define DMC_DDR_t_XSR (((Startup_HCLK / 1000 * DDR_tXSR) - 1) / 1000000 + 1) //17, Min 120ns
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#define DMC_DDR_t_ESR DMC_DDR_t_XSR
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#define DMC_DDR_REFRESH_PRD (((Startup_HCLK / 1000 * DDR_tREFRESH) - 1) / 1000000) // TRM 2656
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#define DMC_DDR_USER_CONFIG 1 // 2b01 : mDDR
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.globl _start, processor_id, is_jtag
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_start: b start_code
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/* if we are injected by JTAG, the script sets _istag content to nonzero */
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is_jtag:
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.word 0
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/* it's at a fixed address (+0x8) so we can breakpoint it in the JTAG script
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* we need to go through this hassle because before this moment, SDRAM is not
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* working so we can't prep it from JTAG
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*/
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_steppingstone_done:
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ldr pc, _start_armboot
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_start_armboot:
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.word start_qi
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_TEXT_BASE:
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.word TEXT_BASE
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processor_id:
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.word 0
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.word 0x41129200 /* s3c2442 ID */
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.word 0x410fb760 /* s3c6410 ID */
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/*
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* These are defined in the board-specific linker script.
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*/
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.globl _bss_start
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_bss_start:
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.word __bss_start
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.globl _bss_end
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_bss_end:
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.word _end
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start_code:
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/*
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* set the cpu to SVC32 mode
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*/
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mrs r0,cpsr
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bic r0,r0,#0x1f
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orr r0,r0,#0xd3
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msr cpsr,r0
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/*
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* flush v4 I/D caches
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*/
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mov r0, #0
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mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
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mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
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/*
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* disable MMU stuff and caches
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*/
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
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bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
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orr r0, r0, #0x00000002 @ set bit 2 (A) Align
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orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
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mcr p15, 0, r0, c1, c0, 0
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/* Peri port setup */
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ldr r0, =0x70000000
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orr r0, r0, #0x13
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mcr p15,0,r0,c15,c2,4 @ 256M(0x70000000-0x7fffffff)
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ldr r0, =ELFIN_MEM_SYS_CFG @Memory sussystem address 0x7e00f120
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mov r1, #0xd @ Xm0CSn2 = NFCON CS0, Xm0CSn3 = NFCON CS1
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str r1, [r0]
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ldr r0, =ELFIN_DMC1_BASE @DMC1 base address 0x7e001000
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ldr r1, =0x04
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str r1, [r0, #INDEX_DMC_MEMC_CMD]
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ldr r1, =DMC_DDR_REFRESH_PRD
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str r1, [r0, #INDEX_DMC_REFRESH_PRD]
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ldr r1, =DMC_DDR_CAS_LATENCY
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str r1, [r0, #INDEX_DMC_CAS_LATENCY]
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ldr r1, =DMC_DDR_t_DQSS
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str r1, [r0, #INDEX_DMC_T_DQSS]
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ldr r1, =DMC_DDR_t_MRD
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str r1, [r0, #INDEX_DMC_T_MRD]
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ldr r1, =DMC_DDR_t_RAS
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str r1, [r0, #INDEX_DMC_T_RAS]
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ldr r1, =DMC_DDR_t_RC
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str r1, [r0, #INDEX_DMC_T_RC]
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ldr r1, =DMC_DDR_t_RCD
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ldr r2, =DMC_DDR_schedule_RCD
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orr r1, r1, r2
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str r1, [r0, #INDEX_DMC_T_RCD]
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ldr r1, =DMC_DDR_t_RFC
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ldr r2, =DMC_DDR_schedule_RFC
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orr r1, r1, r2
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str r1, [r0, #INDEX_DMC_T_RFC]
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ldr r1, =DMC_DDR_t_RP
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ldr r2, =DMC_DDR_schedule_RP
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orr r1, r1, r2
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str r1, [r0, #INDEX_DMC_T_RP]
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ldr r1, =DMC_DDR_t_RRD
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str r1, [r0, #INDEX_DMC_T_RRD]
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ldr r1, =DMC_DDR_t_WR
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str r1, [r0, #INDEX_DMC_T_WR]
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ldr r1, =DMC_DDR_t_WTR
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str r1, [r0, #INDEX_DMC_T_WTR]
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ldr r1, =DMC_DDR_t_XP
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str r1, [r0, #INDEX_DMC_T_XP]
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ldr r1, =DMC_DDR_t_XSR
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str r1, [r0, #INDEX_DMC_T_XSR]
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ldr r1, =DMC_DDR_t_ESR
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str r1, [r0, #INDEX_DMC_T_ESR]
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ldr r1, =DMC1_MEM_CFG
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str r1, [r0, #INDEX_DMC_MEMORY_CFG]
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ldr r1, =DMC1_MEM_CFG2
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str r1, [r0, #INDEX_DMC_MEMORY_CFG2]
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ldr r1, =DMC1_CHIP0_CFG
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str r1, [r0, #INDEX_DMC_CHIP_0_CFG]
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ldr r1, =DMC_DDR_32_CFG
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str r1, [r0, #INDEX_DMC_USER_CONFIG]
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@DMC0 DDR Chip 0 configuration direct command reg
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ldr r1, =DMC_NOP0
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str r1, [r0, #INDEX_DMC_DIRECT_CMD]
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@Precharge All
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ldr r1, =DMC_PA0
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str r1, [r0, #INDEX_DMC_DIRECT_CMD]
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@Auto Refresh 2 time
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ldr r1, =DMC_AR0
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str r1, [r0, #INDEX_DMC_DIRECT_CMD]
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str r1, [r0, #INDEX_DMC_DIRECT_CMD]
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@MRS
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ldr r1, =DMC_mDDR_EMR0
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str r1, [r0, #INDEX_DMC_DIRECT_CMD]
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@Mode Reg
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ldr r1, =DMC_mDDR_MR0
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str r1, [r0, #INDEX_DMC_DIRECT_CMD]
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#if S3C6410_POP_A
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ldr r1, =DMC1_CHIP1_CFG
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str r1, [r0, #INDEX_DMC_CHIP_1_CFG]
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@DMC0 DDR Chip 0 configuration direct command reg
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ldr r1, =DMC_NOP1
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str r1, [r0, #INDEX_DMC_DIRECT_CMD]
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@Precharge All
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ldr r1, =DMC_PA1
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str r1, [r0, #INDEX_DMC_DIRECT_CMD]
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@Auto Refresh 2 time
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ldr r1, =DMC_AR1
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str r1, [r0, #INDEX_DMC_DIRECT_CMD]
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str r1, [r0, #INDEX_DMC_DIRECT_CMD]
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@MRS
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ldr r1, =DMC_mDDR_EMR1
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str r1, [r0, #INDEX_DMC_DIRECT_CMD]
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@Mode Reg
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ldr r1, =DMC_mDDR_MR1
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str r1, [r0, #INDEX_DMC_DIRECT_CMD]
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#endif
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@Enable DMC1
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mov r1, #0x0
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str r1, [r0, #INDEX_DMC_MEMC_CMD]
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check_dmc1_ready:
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ldr r1, [r0, #INDEX_DMC_MEMC_STATUS]
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mov r2, #0x3
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and r1, r1, r2
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cmp r1, #0x1
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bne check_dmc1_ready
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nop
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ldr r0, =ELFIN_CLOCK_POWER_BASE @0x7e00f000
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ldr r1, [r0, #OTHERS_OFFSET]
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mov r2, #0x40
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orr r1, r1, r2
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str r1, [r0, #OTHERS_OFFSET]
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nop
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nop
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nop
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nop
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nop
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ldr r2, =0x80
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orr r1, r1, r2
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str r1, [r0, #OTHERS_OFFSET]
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check_syncack:
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ldr r1, [r0, #OTHERS_OFFSET]
|
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ldr r2, =0xf00
|
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and r1, r1, r2
|
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cmp r1, #0xf00
|
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bne check_syncack
|
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|
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mov r1, #0xff00
|
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orr r1, r1, #0xff
|
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str r1, [r0, #APLL_LOCK_OFFSET]
|
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str r1, [r0, #MPLL_LOCK_OFFSET]
|
||||
str r1, [r0, #EPLL_LOCK_OFFSET]
|
||||
/* CLKUART(=66.5Mhz) = CLKUART_input(532/2=266Mhz) / (UART_RATIO(3)+1) */
|
||||
/* CLKUART(=50Mhz) = CLKUART_input(400/2=200Mhz) / (UART_RATIO(3)+1) */
|
||||
/* Now, When you use UART CLK SRC by EXT_UCLK1, We support 532MHz & 400MHz value */
|
||||
|
||||
ldr r1, [r0, #CLK_DIV2_OFFSET]
|
||||
bic r1, r1, #0x70000
|
||||
orr r1, r1, #0x30000
|
||||
str r1, [r0, #CLK_DIV2_OFFSET]
|
||||
|
||||
|
||||
ldr r1, [r0, #CLK_DIV0_OFFSET] /*Set Clock Divider*/
|
||||
bic r1, r1, #0x30000
|
||||
bic r1, r1, #0xff00
|
||||
bic r1, r1, #0xff
|
||||
ldr r2, =CLK_DIV_VAL
|
||||
orr r1, r1, r2
|
||||
str r1, [r0, #CLK_DIV0_OFFSET]
|
||||
|
||||
ldr r1, =APLL_VAL
|
||||
str r1, [r0, #APLL_CON_OFFSET]
|
||||
ldr r1, =MPLL_VAL
|
||||
str r1, [r0, #MPLL_CON_OFFSET]
|
||||
|
||||
ldr r1, =0x80200203 /* FOUT of EPLL is 96MHz */
|
||||
str r1, [r0, #EPLL_CON0_OFFSET]
|
||||
ldr r1, =0x0
|
||||
str r1, [r0, #EPLL_CON1_OFFSET]
|
||||
|
||||
ldr r1, [r0, #CLK_SRC_OFFSET] /* APLL, MPLL, EPLL select to Fout */
|
||||
|
||||
ldr r2, =0x2007
|
||||
orr r1, r1, r2
|
||||
|
||||
str r1, [r0, #CLK_SRC_OFFSET]
|
||||
|
||||
/* wait at least 200us to stablize all clock */
|
||||
mov r1, #0x10000
|
||||
1: subs r1, r1, #1
|
||||
bne 1b
|
||||
|
||||
ldr r1, [r0, #OTHERS_OFFSET]
|
||||
orr r1, r1, #0x20
|
||||
str r1, [r0, #OTHERS_OFFSET]
|
||||
|
||||
|
||||
/* set GPIO to enable UART */
|
||||
@ GPIO setting for UART
|
||||
ldr r0, =ELFIN_GPIO_BASE
|
||||
ldr r1, =0x220022
|
||||
str r1, [r0, #GPACON_OFFSET]
|
||||
|
||||
ldr r0, =ELFIN_UART_CONSOLE_BASE @0x7F005000
|
||||
mov r1, #0x0
|
||||
str r1, [r0, #UFCON_OFFSET]
|
||||
str r1, [r0, #UMCON_OFFSET]
|
||||
|
||||
mov r1, #0x3 @was 0.
|
||||
str r1, [r0, #ULCON_OFFSET]
|
||||
|
||||
ldr r1, =0xe45 /* UARTCLK SRC = 11 => EXT_UCLK1*/
|
||||
|
||||
str r1, [r0, #UCON_OFFSET]
|
||||
|
||||
ldr r1, =0x22
|
||||
str r1, [r0, #UBRDIV_OFFSET]
|
||||
|
||||
ldr r1, =0x1FFF
|
||||
str r1, [r0, #UDIVSLOT_OFFSET]
|
||||
|
||||
ldr r1, =0x4f4f4f4f
|
||||
str r1, [r0, #UTXH_OFFSET] @'O'
|
||||
|
||||
/* send out a char to say hello */
|
||||
ldr r1, =0x55
|
||||
str r1, [r0, #UTXH_OFFSET]
|
||||
|
||||
|
||||
#if 0
|
||||
/* Below code is for ARM926EJS and ARM1026EJS */
|
||||
.globl cleanDCache
|
||||
cleanDCache:
|
||||
mrc p15, 0, pc, c7, c10, 3 /* test/clean D-Cache */
|
||||
bne cleanDCache
|
||||
mov pc, lr
|
||||
|
||||
.globl cleanFlushDCache
|
||||
cleanFlushDCache:
|
||||
mrc p15, 0, pc, c7, c14, 3 /* test/cleanflush D-Cache */
|
||||
bne cleanFlushDCache
|
||||
mov pc, lr
|
||||
|
||||
.globl cleanFlushCache
|
||||
cleanFlushCache:
|
||||
mrc p15, 0, pc, c7, c14, 3 /* test/cleanflush D-Cache */
|
||||
bne cleanFlushCache
|
||||
mcr p15, 0, r0, c7, c5, 0 /* flush I-Cache */
|
||||
mov pc, lr
|
||||
|
||||
.ltorg
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
|
||||
/* enable only CPU peripheral block clocks we actually use */
|
||||
ldr r0, =0x4c00000c /* clkcon */
|
||||
ldr r1, =0x3f10 /* uart, pwm, gpio, nand, sdi clocks on */
|
||||
str r1, [r0]
|
||||
|
||||
/* gpio UART2 init, H port */
|
||||
ldr r0, =0x56000070
|
||||
ldr r1, =0x001AAAAA
|
||||
str r1, [r0]
|
||||
|
||||
/* enable KEEPACT(GPJ8) to make sure PMU keeps us alive */
|
||||
ldr r0, =0x56000000 /* GPJ base */
|
||||
ldr r1, [r0, #0xd0] /* GPJCON */
|
||||
orr r1, r1, #(1 << 16)
|
||||
str r1, [r0, #0xd0]
|
||||
|
||||
ldr r1, [r0, #0xd4] /* GPJDAT */
|
||||
orr r1, r1, #(1 << 8)
|
||||
str r1, [r0, #0xd4]
|
||||
|
||||
|
||||
|
||||
/* take sdram out of power down */
|
||||
ldr r0, =0x56000080 /* misccr */
|
||||
ldr r1, [ r0 ]
|
||||
bic r1, r1, #(S3C2410_MISCCR_nEN_SCLK0 | S3C2410_MISCCR_nEN_SCLK1 | S3C2410_MISCCR_nEN_SCLKE)
|
||||
str r1, [ r0 ]
|
||||
|
||||
/* ensure signals stabalise */
|
||||
mov r1, #128
|
||||
1: subs r1, r1, #1
|
||||
bpl 1b
|
||||
|
||||
bl cpu_init_crit
|
||||
|
||||
/* ensure some refresh has happened */
|
||||
ldr r1, =0xfffff
|
||||
1: subs r1, r1, #1
|
||||
bpl 1b
|
||||
|
||||
/* capture full EINT situation into gstatus 4 */
|
||||
|
||||
ldr r0, =0x4A000000 /* SRCPND */
|
||||
ldr r1, [ r0 ]
|
||||
and r1, r1, #0xf
|
||||
|
||||
ldr r0, =0x560000BC /* gstatus4 */
|
||||
str r1, [ r0 ]
|
||||
|
||||
ldr r0, =0x560000A8 /* EINTPEND */
|
||||
ldr r1, [ r0 ]
|
||||
ldr r0, =0xfff0
|
||||
and r1, r1, r0
|
||||
ldr r0, =0x560000BC /* gstatus4 */
|
||||
ldr r0, [ r0 ]
|
||||
orr r1, r1, r0
|
||||
ldr r0, =0x560000BC /* gstatus4 */
|
||||
str r1, [ r0 ]
|
||||
|
||||
/* test for resume */
|
||||
|
||||
ldr r1, =0x560000B4 /* gstatus2 */
|
||||
ldr r0, [ r1 ]
|
||||
tst r0, #0x02 /* is this resume from power down */
|
||||
/* well, if it was, we are going to jump to
|
||||
* whatever address we stashed in gstatus3,
|
||||
* and gstatus4 will hold the wake interrupt
|
||||
* source for the OS to look at
|
||||
*/
|
||||
ldrne pc, [r1, #4]
|
||||
|
||||
#endif
|
||||
|
||||
/* >> CFG_VIDEO_LOGO_MAX_SIZE */
|
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
|
||||
|
||||
stack_setup:
|
||||
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
|
||||
sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
|
||||
sub sp, r0, #12 /* leave 3 words for abort-stack */
|
||||
|
||||
clear_bss:
|
||||
ldr r0, _bss_start /* find start of bss segment */
|
||||
ldr r1, _bss_end /* stop here */
|
||||
mov r2, #0x00000000 /* clear */
|
||||
|
||||
clbss_l:
|
||||
str r2, [r0] /* clear loop... */
|
||||
add r0, r0, #4
|
||||
cmp r0, r1
|
||||
ble clbss_l
|
||||
|
||||
/* we are going to jump into the C part of the init now */
|
||||
spin:
|
||||
b _steppingstone_done
|
||||
Reference in New Issue
Block a user