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add neo_gta02.h lowlevel_init.S and kboot-stage1.lds

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xiangfu 2008-06-17 10:40:22 -04:00
parent 280f8ffb13
commit d076efdbe7
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306
qiboot/include/neo_gta02.h Normal file
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/*
* (C) Copyright 2007 OpenMoko, Inc.
* Author: Harald Welte <laforge@openmoko.org>
*
* Configuation settings for the FIC Neo1973 GTA02 Linux GSM phone
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define TEXT_BASE 0x00000000 /* xiangfu add*/
/* we want to be able to start u-boot directly from within NAND flash */
#define CONFIG_LL_INIT_NAND_ONLY
#define CONFIG_S3C2410_NAND_BOOT 1
#define CONFIG_S3C2410_NAND_SKIP_BAD 1
#define CFG_UBOOT_SIZE 0x40000 /* size of u-boot, for NAND loading */
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
#define CONFIG_SMDK2440 1 /* on a SAMSUNG SMDK2410 Board */
/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ 12000000/* the GTA02 has this input clock */
#define USE_920T_MMU 1
#define CONFIG_USE_IRQ 1
/*
* Size of malloc() pool
*/
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 400*1024)
/* >> CFG_VIDEO_LOGO_MAX_SIZE */
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
* Hardware drivers
*/
/*
* select serial console configuration
*/
#define CONFIG_SERIAL3 1 /* we use SERIAL 1 on GTA01 */
#define CONFIG_SERIAL_MULTI
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 115200
/***********************************************************
* Command definition
***********************************************************/
#define CONFIG_CMD_BDI
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_IMI
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_ENV
/* CFG_CMD_IRQ | */ \
#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_CONSOLE
/* CFG_CMD_BMP | */ \
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_RUN
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_I2C
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_AUTOSCRIPT
#define CONFIG_CMD_BSP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_MISC
/* CFG_CMD_USB | */ \
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_DIAG
/* CFG_CMD_HWFLOW | */ \
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_NAND
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_PORTIO
#define CONFIG_CMD_MMC
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_LICENSE
#define CONFIG_CMD_TERMINAL
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS ""
#define CONFIG_BOOTCOMMAND "setenv bootargs ${bootargs_base} ${mtdparts}; nand read.e 0x32000000 kernel; bootm 0x32000000"
#define CONFIG_DOS_PARTITION 1
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
/* what's this ? it's not used anywhere */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
#endif
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define STRINGIFY(s) DO_STRINGIFY(s) /* expand the argument */
#define DO_STRINGIFY(s) #s /* quote it */
#define CFG_PROMPT __cfg_prompt
/* Monitor Command Prompt */
#ifndef __ASSEMBLY__
/*extern char __cfg_prompt[20];*/
#endif
#if defined(CONFIG_ARCH_GTA02_v1)
#define CONFIG_S3C2440 1 /* SAMSUNG S3C2440 SoC */
#else
#define CONFIG_S3C2442 1 /* SAMSUNG S3C2442 SoC */
#endif
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 64 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x30000000 /* memtest works on */
#define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CFG_LOAD_ADDR 0x33000000 /* default load address */
/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
/* it to wrap 100 times (total 1562500) to get 1 sec. */
#define CFG_HZ 1562500
/* valid baudrates */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CFG_BOOTMENU
/*-----------------------------------------------------------------------
* Stack sizes
*
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
#endif
#if 0
#define CONFIG_USB_OHCI_NEW 1
#define CFG_USB_OHCI_CPU_INIT 1
#define CFG_USB_OHCI_REGS_BASE 0x49000000 /* S3C24X0_USB_HOST_BASE */
#define CFG_USB_OHCI_SLOT_NAME "s3c2440"
#define CFG_USB_OHCI_MAX_ROOT_PORTS 2
#endif
#define CONFIG_USB_DEVICE 1
#define CONFIG_USB_TTY 1
#define CFG_CONSOLE_IS_IN_ENV 1
#define CONFIG_USBD_VENDORID 0x1d50 /* OpenMoko, Inc. */
#define CONFIG_USBD_PRODUCTID_GSERIAL 0x5120 /* gserial */
#define CONFIG_USBD_PRODUCTID_CDCACM 0x5119 /* CDC ACM */
#define CONFIG_USBD_MANUFACTURER "OpenMoko, Inc"
#define CONFIG_USBD_PRODUCT_NAME "Neo1973 Bootloader " U_BOOT_VERSION
#define CONFIG_USBD_DFU 1
#define CONFIG_USBD_DFU_XFER_SIZE 4096 /* 0x4000 */
#define CONFIG_USBD_DFU_INTERFACE 2
#define CONFIG_EXTRA_ENV_SETTINGS \
"usbtty=cdc_acm\0" \
"stderr=usbtty\0stdout=usbtty\0stdin=usbtty\0" \
"bootargs_base=rootfstype=jffs2 root=/dev/mtdblock6 console=ttySAC2,115200 console=tty0 loglevel=8\0" \
""
#define CONFIG_CMD_LOADENV
#define CONFIG_CMD_DEFAULTENV
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
#define PHYS_SDRAM_RES_SIZE 0x00200000 /* 2 MB for frame buffer */
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
#define CFG_ENV_IS_IN_NAND 1
#define CFG_ENV_SIZE 0x40000 /* 128k Total Size of Environment Sector */
#define CFG_ENV_OFFSET_OOB 1 /* Location of ENV stored in block 0 OOB */
#define CFG_PREBOOT_OVERRIDE 1 /* allow preboot from memory */
#define CFG_ENV_OVERRIDE /* allow pre-loading the environment */
#define NAND_MAX_CHIPS 1
#define CFG_NAND_BASE 0x4e000000
#define CFG_MAX_NAND_DEVICE 1
#define CONFIG_MMC 1
#define CONFIG_MMC_WIDE 1
#define CONFIG_MMC_GLAMO 1
#define CFG_MMC_BASE 0xff000000
#define CONFIG_DEPOWER_MMC_ON_BOOT 1
/* EXT2 driver */
#define CONFIG_EXT2 1
#define CONFIG_FAT 1
#define CONFIG_SUPPORT_VFAT
#if 1
/* JFFS2 driver */
#define CONFIG_JFFS2_CMDLINE 1
#define CONFIG_JFFS2_NAND 1
#define CONFIG_JFFS2_NAND_DEV 0
//#define CONFIG_JFFS2_NAND_OFF 0x634000
//#define CONFIG_JFFS2_NAND_SIZE 0x39cc000
#endif
/* ATAG configuration */
#define CONFIG_INITRD_TAG 1
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_CMDLINE_TAG 1
#define CONFIG_REVISION_TAG 1
#if 0
#define CONFIG_SERIAL_TAG 1
#endif
#define CONFIG_DRIVER_S3C24X0_I2C 1
#define CONFIG_HARD_I2C 1
#define CFG_I2C_SPEED 400000 /* 400kHz according to PCF50633 data sheet */
#define CFG_I2C_SLAVE 0x7f
/* we have a board_late_init() function */
#define BOARD_LATE_INIT 1
#if 1
#define CONFIG_VIDEO
#define CONFIG_VIDEO_GLAMO3362
#define CONFIG_CFB_CONSOLE
//#define CONFIG_VIDEO_LOGO
//#define CONFIG_SPLASH_SCREEN
#define CFG_VIDEO_LOGO_MAX_SIZE (640*480+1024+100) /* 100 = slack */
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_CMD_UNZIP
#define VIDEO_FB_16BPP_PIXEL_SWAP
#define VIDEO_KBD_INIT_FCT 0
#define VIDEO_TSTC_FCT serial_tstc
#define VIDEO_GETC_FCT serial_getc
#define CONFIG_GLAMO_BASE 0x08000000
#endif
#define CONFIG_S3C2410_NAND_BBT 1
//#define CONFIG_S3C2410_NAND_HWECC 1
#define CONFIG_DRIVER_PCF50633 1
#define CONFIG_RTC_PCF50633 1
#define MTDIDS_DEFAULT "nor0=physmap-flash,nand0=neo1973-nand"
//#define MTPARTS_DEFAULT "neo1973-nand:256k(u-boot),128k(u-boot_env),8M(kernel),640k(splash),256k(factory),-(rootfs)"
#define CFG_MTDPARTS_PREFIX "physmap-flash:-(nor);"
#define CFG_NAND_DYNPART_MTD_KERNEL_NAME "neo1973-nand"
#define CONFIG_NAND_DYNPART
#define CFG_MAX_FLASH_BANKS 1
#define CFG_MAX_FLASH_SECT 1
#define DFU_NUM_ALTERNATES 7
#ifndef __ASSEMBLY__
/*extern int gta02_revision;*/ /* use this instead of CONFIG_GTA02_REVISION */
#endif
#endif /* __CONFIG_H */

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qiboot/src/kboot.lds Normal file
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/*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
led_S.o (.text)
led_C.o (.text)
*(.text)
}
. = ALIGN(4);
.rodata : { *(.rodata) }
. = ALIGN(4);
.data : { *(.data) }
. = ALIGN(4);
.got : { *(.got) }
. = ALIGN(4);
__bss_start = .;
.bss (NOLOAD) : { *(.bss) }
_end = .;
}

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qiboot/src/lowlevel_init.S Normal file
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/*
* Memory Setup stuff - taken from blob memsetup.S
*
* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
*
* Modified for the FIC Neo1973 GTA01 by Harald Welte <laforge@openmoko.org>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* #include <config.h>
* #include <version.h>
*/
#include <neo_gta02.h>
/* some parameters for the board */
/*
*
* Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
*
* Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar@sec.samsung.com>
*
*/
#define BWSCON 0x48000000
/* BWSCON */
#define DW8 (0x0)
#define DW16 (0x1)
#define DW32 (0x2)
#define WAIT (0x1<<2)
#define UBLB (0x1<<3)
#define B1_BWSCON (DW16 + WAIT + UBLB)
#define B2_BWSCON (DW16)
#define B3_BWSCON (DW16 + WAIT + UBLB)
#define B4_BWSCON (DW16)
#define B5_BWSCON (DW16)
#define B6_BWSCON (DW32)
#define B7_BWSCON (DW32)
/* BANK0CON */
#define B0_Tacs 0x0 /* 0clk */
#define B0_Tcos 0x0 /* 0clk */
#define B0_Tacc 0x7 /* 14clk */
#define B0_Tcoh 0x0 /* 0clk */
#define B0_Tah 0x0 /* 0clk */
#define B0_Tacp 0x0
#define B0_PMC 0x0 /* normal */
/* BANK1CON: Smedia Glamo 3362 (on GTA02) */
#define B1_Tacs 0x0 /* 0clk */
#define B1_Tcos 0x3 /* 4clk */
#define B1_Tacc 0x3 /* 4clk */
#define B1_Tcoh 0x3 /* 4clk */
#define B1_Tah 0x0 /* 0clk */
#define B1_Tacp 0x0
#define B1_PMC 0x0
#define B2_Tacs 0x0
#define B2_Tcos 0x0
#define B2_Tacc 0x7
#define B2_Tcoh 0x0
#define B2_Tah 0x0
#define B2_Tacp 0x0
#define B2_PMC 0x0
#define B3_Tacs 0x0 /* 0clk */
#define B3_Tcos 0x3 /* 4clk */
#define B3_Tacc 0x7 /* 14clk */
#define B3_Tcoh 0x1 /* 1clk */
#define B3_Tah 0x0 /* 0clk */
#define B3_Tacp 0x3 /* 6clk */
#define B3_PMC 0x0 /* normal */
#define B4_Tacs 0x0 /* 0clk */
#define B4_Tcos 0x0 /* 0clk */
#define B4_Tacc 0x7 /* 14clk */
#define B4_Tcoh 0x0 /* 0clk */
#define B4_Tah 0x0 /* 0clk */
#define B4_Tacp 0x0
#define B4_PMC 0x0 /* normal */
#define B5_Tacs 0x0 /* 0clk */
#define B5_Tcos 0x0 /* 0clk */
#define B5_Tacc 0x7 /* 14clk */
#define B5_Tcoh 0x0 /* 0clk */
#define B5_Tah 0x0 /* 0clk */
#define B5_Tacp 0x0
#define B5_PMC 0x0 /* normal */
#define B6_MT 0x3 /* SDRAM */
#define B6_Trcd 0x1 /* 3clk */
#define B6_SCAN 0x1 /* 9bit */
#define B7_SCAN 0x1 /* 9bit */
#define B7_MT 0x3 /* SDRAM */
#define B7_Trcd 0x1 /* 3clk */
/* REFRESH parameter */
#define REFEN 0x1 /* Refresh enable */
#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
#define Trp 0x1 /* 3clk */
#define Trc 0x3 /* 7clk */
#define Tchr 0x2 /* 3clk */
//#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
#define REFCNT 997 /* period=17.5us, HCLK=60Mhz, (2048+1-15.6*60) */
/**************************************/
_TEXT_BASE:
.word TEXT_BASE
.globl lowlevel_init
lowlevel_init:
/* memory control configuration */
/* make r0 relative the current location so that it */
/* reads SMRDATA out of FLASH rather than memory ! */
adr r0, SMRDATA
ldr r1, =BWSCON /* Bus Width Status Controller */
add r2, r0, #13*4
0:
ldr r3, [r0], #4
str r3, [r1], #4
cmp r2, r0
bne 0b
/* setup asynchronous bus mode */
mrc p15, 0, r1 ,c1 ,c0, 0
orr r1, r1, #0xc0000000
mcr p15, 0, r1, c1, c0, 0
#if defined(CONFIG_ARCH_GTA01_v4) || defined(CONFIG_ARCH_GTA01B_v2) || defined(CONFIG_ARCH_GTA01B_v3)
/* switch on power for NAND */
ldr r0, =0x56000010 /* GPBCON */
ldr r1, [r0]
orr r1, r1, #0x10
str r1, [r0]
ldr r0, =0x56000014 /* GPBDAT */
ldr r1, [r0]
orr r1, r1, #(1 <<2)
str r1, [r0]
#endif
#if defined(CONFIG_ARCH_GTA02_v1)
/* enable KEEPACT(GPJ3) to make sure PMU keeps us alive */
ldr r0, =0x56000000 /* GPJ base */
ldr r1, [r0, #0xd0] /* GPJCON */
orr r1, r1, #(1 << 6)
str r1, [r0, #0xd0]
ldr r1, [r0, #0xd4] /* GPJDAT */
orr r1, r1, #(1 << 3)
str r1, [r0, #0xd4]
#elif CONFIG_GTA02_REVISION >= 2
/* enable KEEPACT(GPJ8) to make sure PMU keeps us alive */
ldr r0, =0x56000000 /* GPJ base */
ldr r1, [r0, #0xd0] /* GPJCON */
orr r1, r1, #(1 << 16)
str r1, [r0, #0xd0]
ldr r1, [r0, #0xd4] /* GPJDAT */
orr r1, r1, #(1 << 8)
str r1, [r0, #0xd4]
#endif
/* everything is fine now */
mov pc, lr
.ltorg
/* the literal pools origin */
SMRDATA:
.word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
.word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
.word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
.word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
.word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
.word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
.word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
.word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
.word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
.word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
#if CONFIG_GTA02_REVISION >= 2
.word 0xb1
#else
.word 0xb2
#endif
.word 0x30
.word 0x30