mirror of
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82d2e255c3
This heavily adapts the Samsung U-Boot hs_mmc code and combines it with the SD / SDHC startup code written for glamo-mci stuff that is known to work OK with common SD and SDHC. tla01 is changed to use the implementation. Signed-off-by: Andy Green <andy@openmoko.com>
383 lines
13 KiB
C
383 lines
13 KiB
C
/*
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* Header for MultiMediaCard (MMC)
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*
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* Copyright 2002 Hewlett-Packard Company
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*
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* Use consistent with the GNU GPL is permitted,
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* provided that this copyright notice is
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* preserved in its entirety in all copies and derived works.
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*
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* HEWLETT-PACKARD COMPANY MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
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* AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
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* FITNESS FOR ANY PARTICULAR PURPOSE.
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*
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* Many thanks to Alessandro Rubini and Jonathan Corbet!
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*
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* Based strongly on code by:
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*
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* Author: Yong-iL Joh <tolkien@mizi.com>
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* Date : $Date: 2006/12/06 02:50:52 $
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*
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* Author: Andrew Christian
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* 15 May 2002
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*/
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#ifndef MMC_MMC_PROTOCOL_H
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#define MMC_MMC_PROTOCOL_H
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#ifdef CONFIG_SUPPORT_MMC_PLUS
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/* Standard MMC commands (4.2) type argument response */
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#else
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/* Standard MMC commands (3.1) type argument response */
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#endif
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/* class 1 */
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#define MMC_GO_IDLE_STATE 0 /* bc */
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#define MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */
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#define MMC_ALL_SEND_CID 2 /* bcr R2 */
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#define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */
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#define MMC_SET_DSR 4 /* bc [31:16] RCA */
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#define MMC_SWITCH 6 /* ac R1b */
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#define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */
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#define MMC_SEND_EXT_CSD 8 /* adtc R1 */
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#define MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */
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#define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */
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#define MMC_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */
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#define MMC_STOP_TRANSMISSION 12 /* ac R1b */
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#define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */
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#define MMC_BUSTEST_R 14 /* adtc R1 */
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#define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */
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#define MMC_BUSTEST_W 19 /* adtc R1 */
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/* class 2 */
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#define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */
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#define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */
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#define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */
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/* class 3 */
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#define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */
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/* class 4 */
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#define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */
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#define MMC_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */
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#define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */
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#define MMC_PROGRAM_CID 26 /* adtc R1 */
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#define MMC_PROGRAM_CSD 27 /* adtc R1 */
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/* class 6 */
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#define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */
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#define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */
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#define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */
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/* class 5 */
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#define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */
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#define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */
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#define MMC_ERASE 38 /* ac R1b */
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/* class 9 */
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#define MMC_FAST_IO 39 /* ac <Complex> R4 */
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#define MMC_GO_IRQ_STATE 40 /* bcr R5 */
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/* class 7 */
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#define MMC_LOCK_UNLOCK 42 /* adtc R1b */
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/* class 8 */
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#define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */
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#define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1 */
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/* SD commands type argument response */
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/* class 8 */
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/* This is basically the same command as for MMC with some quirks. */
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#define SD_SEND_RELATIVE_ADDR 3 /* ac R6 */
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/* Application commands */
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#define SD_APP_SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */
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#define SD_APP_OP_COND 41 /* bcr [31:0] OCR R3 */
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#define SD_APP_SEND_SCR 51 /* adtc R1 */
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/*
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MMC status in R1
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Type
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e : error bit
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s : status bit
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r : detected and set for the actual command response
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x : detected and set during command execution. the host must poll
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the card by sending status command in order to read these bits.
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Clear condition
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a : according to the card state
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b : always related to the previous command. Reception of
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a valid command will clear it (with a delay of one command)
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c : clear by read
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*/
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#define R1_OUT_OF_RANGE (1 << 31) /* er, c */
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#define R1_ADDRESS_ERROR (1 << 30) /* erx, c */
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#define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */
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#define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */
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#define R1_ERASE_PARAM (1 << 27) /* ex, c */
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#define R1_WP_VIOLATION (1 << 26) /* erx, c */
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#define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */
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#define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */
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#define R1_COM_CRC_ERROR (1 << 23) /* er, b */
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#define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */
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#define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */
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#define R1_CC_ERROR (1 << 20) /* erx, c */
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#define R1_ERROR (1 << 19) /* erx, c */
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#define R1_UNDERRUN (1 << 18) /* ex, c */
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#define R1_OVERRUN (1 << 17) /* ex, c */
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#define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */
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#define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */
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#define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */
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#define R1_ERASE_RESET (1 << 13) /* sr, c */
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#define R1_STATUS(x) (x & 0xFFFFE000)
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#define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */
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#define R1_READY_FOR_DATA (1 << 8) /* sx, a */
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#define R1_APP_CMD (1 << 5) /* sr, c */
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/*
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MMC CURRENT_STATE in R1 [12:9]
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*/
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#define STATE_IDLE (0x0 << 9) /* 0 */
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#define STATE_READY (0x1 << 9) /* 1 */
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#define STATE_IDENT (0x2 << 9) /* 2 */
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#define STATE_STBY (0x3 << 9) /* 3 */
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#define STATE_TRAN (0x4 << 9) /* 4 */
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#define STATE_DATA (0x5 << 9) /* 5 */
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#define STATE_RCV (0x6 << 9) /* 6 */
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#define STATE_PRG (0x7 << 9) /* 7 */
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#define STATE_DIS (0x8 << 9) /* 8 */
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#define STATE_BTST (0x9 << 9) /* 9 */
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/* These are unpacked versions of the actual responses */
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struct _mmc_csd {
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u8 csd_structure;
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u8 spec_vers;
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u8 taac;
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u8 nsac;
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u8 tran_speed;
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u16 ccc;
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u8 read_bl_len;
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u8 read_bl_partial;
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u8 write_blk_misalign;
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u8 read_blk_misalign;
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u8 dsr_imp;
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u16 c_size;
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u8 vdd_r_curr_min;
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u8 vdd_r_curr_max;
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u8 vdd_w_curr_min;
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u8 vdd_w_curr_max;
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u8 c_size_mult;
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union {
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struct { /* MMC system specification version 3.1 */
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u8 erase_grp_size;
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u8 erase_grp_mult;
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} v31;
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struct { /* MMC system specification version 2.2 */
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u8 sector_size;
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u8 erase_grp_size;
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} v22;
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} erase;
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u8 wp_grp_size;
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u8 wp_grp_enable;
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u8 default_ecc;
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u8 r2w_factor;
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u8 write_bl_len;
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u8 write_bl_partial;
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u8 file_format_grp;
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u8 copy;
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u8 perm_write_protect;
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u8 tmp_write_protect;
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u8 file_format;
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u8 ecc;
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};
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struct _mmc_ext_csd {
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u8 s_cmd_set;
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u32 sec_count;
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u8 MIN_PERF_W_8_52;
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u8 MIN_PERF_R_8_52;
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u8 MIN_PERF_W_8_26_4_52;
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u8 MIN_PERF_R_8_26_4_52;
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u8 MIN_PERF_W_4_26;
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u8 MIN_PERF_R_4_26;
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u8 PWR_CL_26_360;
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u8 PWR_CL_52_360;
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u8 PWR_CL_26_195;
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u8 PWR_CL_52_195;
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u8 card_type;
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u8 csd_structure;
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u8 ext_csd_rev;
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u8 cmd_set;
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u8 cmd_set_rev;
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u8 power_class;
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u8 hs_timing;
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u8 bus_width;
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};
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#define MMC_VDD_145_150 0x00000001 /* VDD voltage 1.45 - 1.50 */
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#define MMC_VDD_150_155 0x00000002 /* VDD voltage 1.50 - 1.55 */
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#define MMC_VDD_155_160 0x00000004 /* VDD voltage 1.55 - 1.60 */
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#define MMC_VDD_160_165 0x00000008 /* VDD voltage 1.60 - 1.65 */
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#define MMC_VDD_165_170 0x00000010 /* VDD voltage 1.65 - 1.70 */
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#define MMC_VDD_17_18 0x00000020 /* VDD voltage 1.7 - 1.8 */
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#define MMC_VDD_18_19 0x00000040 /* VDD voltage 1.8 - 1.9 */
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#define MMC_VDD_19_20 0x00000080 /* VDD voltage 1.9 - 2.0 */
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#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
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#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
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#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
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#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
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#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
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#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
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#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
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#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
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#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
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#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
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#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
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#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
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#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
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#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
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#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
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#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
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#define MMC_CARD_BUSY 0x80000000 /* Card Power up status bit */
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/*
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* Card Command Classes (CCC)
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*/
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#define CCC_BASIC (1<<0) /* (0) Basic protocol functions */
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/* (CMD0,1,2,3,4,7,9,10,12,13,15) */
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#define CCC_STREAM_READ (1<<1) /* (1) Stream read commands */
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/* (CMD11) */
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#define CCC_BLOCK_READ (1<<2) /* (2) Block read commands */
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/* (CMD16,17,18) */
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#define CCC_STREAM_WRITE (1<<3) /* (3) Stream write commands */
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/* (CMD20) */
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#define CCC_BLOCK_WRITE (1<<4) /* (4) Block write commands */
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/* (CMD16,24,25,26,27) */
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#define CCC_ERASE (1<<5) /* (5) Ability to erase blocks */
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/* (CMD32,33,34,35,36,37,38,39) */
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#define CCC_WRITE_PROT (1<<6) /* (6) Able to write protect blocks */
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/* (CMD28,29,30) */
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#define CCC_LOCK_CARD (1<<7) /* (7) Able to lock down card */
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/* (CMD16,CMD42) */
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#define CCC_APP_SPEC (1<<8) /* (8) Application specific */
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/* (CMD55,56,57,ACMD*) */
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#define CCC_IO_MODE (1<<9) /* (9) I/O mode */
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/* (CMD5,39,40,52,53) */
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#define CCC_SWITCH (1<<10) /* (10) High speed switch */
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/* (CMD6,34,35,36,37,50) */
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/* (11) Reserved */
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/* (CMD?) */
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/*
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* CSD field definitions
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*/
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#define CSD_STRUCT_VER_1_0 0 /* Valid for system specification 1.0 - 1.2 */
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#define CSD_STRUCT_VER_1_1 1 /* Valid for system specification 1.4 - 2.2 */
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#define CSD_STRUCT_VER_1_2 2 /* Valid for system specification 3.1 */
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#define CSD_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.2 */
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#define CSD_SPEC_VER_1 1 /* Implements system specification 1.4 */
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#define CSD_SPEC_VER_2 2 /* Implements system specification 2.0 - 2.2 */
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#define CSD_SPEC_VER_3 3 /* Implements system specification 3.1 */
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#define CSD_SPEC_VER_4 4 /* Implements system specification 4.0 ~ 4.2 */
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/*
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* SD bus widths
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*/
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#define SD_BUS_WIDTH_1 0
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#define SD_BUS_WIDTH_4 2
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/*
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* EXT_CSD field definitions
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*/
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/*
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* S_CMD_SET
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*/
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#define STANDARD_MMC 0 /* Standard MMC */
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#define SECURE_MMC 1 /* Secure MMC */
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#define CPS_MMC 2 /* Content Protection Secure MMC */
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#define SECURE_MMC_2 3 /* Secure MMC 2.0 */
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#define ATA_MMC 4 /* ATA on MMC */
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/*
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* MIN_PERF_a_b_ff
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*/
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#define NO_CLASS 0x0 /* For cards not reaching the 2.4MB/s minimum value */
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#define CLASS_A 0x08 /* Class A */
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#define CLASS_B 0x0A /* Class B */
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#define CLASS_C 0x0F /* Class C */
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#define CLASS_D 0x14 /* Class D */
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#define CLASS_E 0x1E /* Class E */
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#define CLASS_F 0x28 /* Class F */
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#define CLASS_G 0x32 /* Class G */
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#define CLASS_H 0x3c /* Class H */
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#define CLASS_J 0x46 /* Class J */
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#define CLASS_K 0x50 /* Class E */
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#define CLASS_M 0x64 /* Class M */
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#define CLASS_O 0x78 /* Class O */
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#define CLASS_R 0x8c /* Class R */
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#define CLASS_T 0xa0 /* Class T */
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/*
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* CARD_TYPE
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*/
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#define MMCPLUS_26MHZ (1<<0)
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#define MMCPLUS_52MHZ (1<<1)
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/*
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* EXT_CSD_REV
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*/
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#define EXT_CSD_REV_1_0 0
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#define EXT_CSD_REV_1_1 1
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#define EXT_CSD_REV_1_2 2
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/*
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* HS_TIMING
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*/
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#define HS_TIMING_LOW 0
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#define HS_TIMING_HIGH 1
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/*
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* BUS_WIDTH
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*/
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#define MMCPLUS_BUS_WIDTH_1 0
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#define MMCPLUS_BUS_WIDTH_4 1
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#define MMCPLUS_BUS_WIDTH_8 2
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/*
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* ERASED_MEM_CONT
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*/
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#define ERASED_MEM_CONT_0 0
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#define ERASED_MEM_CONT_1 1
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/*
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* Argument for CMD6
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*/
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/*
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* EXT_CSD Access Modes
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*/
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#define EXT_CSD_COMMAND_SET 0
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#define EXT_CSD_SET_BITS 1
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#define EXT_CSD_CLEAR_BITS 2
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#define EXT_CSD_WRITE_BYTE 3
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/*
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* EXT_CSD Argument Byte
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*/
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#define EXT_CSD_POWER_CLASS 187
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#define EXT_CSD_BUS_WIDTH 183
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#define EXT_CSD_HS_TIMING 185
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#endif /* MMC_MMC_PROTOCOL_H */
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