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git://projects.qi-hardware.com/xburst-tools.git
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330 lines
7.3 KiB
C
330 lines
7.3 KiB
C
/*
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* jz4740_nand.c
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*
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* NAND read routine for JZ4740
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*
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* Copyright (c) 2005-2008 Ingenic Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <config.h>
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#ifdef CONFIG_JZ4740
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#include <nand.h>
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#include <jz4740.h>
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#define NAND_DATAPORT 0xb8000000
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#define NAND_ADDRPORT 0xb8010000
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#define NAND_COMMPORT 0xb8008000
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#define ECC_BLOCK 512
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#define ECC_POS 6
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#define PAR_SIZE 9
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#define __nand_cmd(n) (REG8(NAND_COMMPORT) = (n))
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#define __nand_addr(n) (REG8(NAND_ADDRPORT) = (n))
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#define __nand_data8() REG8(NAND_DATAPORT)
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#define __nand_data16() REG16(NAND_DATAPORT)
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#define __nand_enable() (REG_EMC_NFCSR |= EMC_NFCSR_NFE1 | EMC_NFCSR_NFCE1)
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#define __nand_disable() (REG_EMC_NFCSR &= ~(EMC_NFCSR_NFCE1))
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#define __nand_ecc_rs_encoding() \
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(REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST | EMC_NFECR_RS | EMC_NFECR_RS_ENCODING)
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#define __nand_ecc_rs_decoding() \
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(REG_EMC_NFECR = EMC_NFECR_ECCE | EMC_NFECR_ERST | EMC_NFECR_RS | EMC_NFECR_RS_DECODING)
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#define __nand_ecc_disable() (REG_EMC_NFECR &= ~EMC_NFECR_ECCE)
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#define __nand_ecc_encode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_ENCF))
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#define __nand_ecc_decode_sync() while (!(REG_EMC_NFINTS & EMC_NFINTS_DECF))
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/*--------------------------------------------------------------*/
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static inline void nand_wait_ready(void)
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{
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unsigned int timeout = 1000;
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while ((REG_GPIO_PXPIN(2) & 0x40000000) && timeout--);
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while (!(REG_GPIO_PXPIN(2) & 0x40000000));
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}
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static inline void nand_read_buf16(void *buf, int count)
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{
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int i;
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u16 *p = (u16 *)buf;
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for (i = 0; i < count; i += 2)
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*p++ = __nand_data16();
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}
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static inline void nand_read_buf8(void *buf, int count)
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{
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int i;
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u8 *p = (u8 *)buf;
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for (i = 0; i < count; i++)
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*p++ = __nand_data8();
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}
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static inline void nand_read_buf(void *buf, int count, int bw)
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{
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if (bw == 8)
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nand_read_buf8(buf, count);
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else
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nand_read_buf16(buf, count);
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}
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/*
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* Correct 1~9-bit errors in 512-bytes data
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*/
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static void rs_correct(unsigned char *dat, int idx, int mask)
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{
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int i, j;
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unsigned short d, d1, dm;
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i = (idx * 9) >> 3;
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j = (idx * 9) & 0x7;
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i = (j == 0) ? (i - 1) : i;
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j = (j == 0) ? 7 : (j - 1);
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if (i > 512) return;
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if (i == 512)
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d = dat[i - 1];
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else
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d = (dat[i] << 8) | dat[i - 1];
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d1 = (d >> j) & 0x1ff;
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d1 ^= mask;
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dm = ~(0x1ff << j);
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d = (d & dm) | (d1 << j);
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dat[i - 1] = d & 0xff;
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if (i < 512)
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dat[i] = (d >> 8) & 0xff;
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}
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/*
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* Read oob
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*/
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static int nand_read_oob(struct nand_param *nandp, int page_addr, u8 *buf, int size)
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{
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int page_size, row_cycle, bus_width;
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int col_addr;
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page_size = nandp->page_size;
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row_cycle = nandp->row_cycle;
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bus_width = nandp->bus_width;
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if (page_size == 2048)
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col_addr = 2048;
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else
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col_addr = 0;
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if (page_size == 2048)
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/* Send READ0 command */
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__nand_cmd(NAND_CMD_READ0);
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else
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/* Send READOOB command */
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__nand_cmd(NAND_CMD_READOOB);
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/* Send column address */
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__nand_addr(col_addr & 0xff);
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if (page_size == 2048)
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__nand_addr((col_addr >> 8) & 0xff);
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/* Send page address */
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__nand_addr(page_addr & 0xff);
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__nand_addr((page_addr >> 8) & 0xff);
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if (row_cycle == 3)
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__nand_addr((page_addr >> 16) & 0xff);
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/* Send READSTART command for 2048 ps NAND */
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if (page_size == 2048)
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__nand_cmd(NAND_CMD_READSTART);
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/* Wait for device ready */
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nand_wait_ready();
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/* Read oob data */
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nand_read_buf(buf, size, bus_width);
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return 0;
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}
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/*
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* nand_read_page()
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*
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* Input:
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*
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* nandp - pointer to nand info
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* block - block number: 0, 1, 2, ...
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* page - page number within a block: 0, 1, 2, ...
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* dst - pointer to target buffer
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*/
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int nand_read_page(struct nand_param *nandp, int block, int page, u8 *dst)
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{
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int page_size, oob_size, page_per_block;
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int row_cycle, bus_width, ecc_count;
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int page_addr, i, j;
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u8 *data_buf;
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u8 oob_buf[64];
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page_size = nandp->page_size;
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oob_size = nandp->oob_size;
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page_per_block = nandp->page_per_block;
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row_cycle = nandp->row_cycle;
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bus_width = nandp->bus_width;
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page_addr = page + block * page_per_block;
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/*
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* Read oob data
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*/
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nand_read_oob(nandp, page_addr, oob_buf, oob_size);
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/*
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* Read page data
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*/
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/* Send READ0 command */
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__nand_cmd(NAND_CMD_READ0);
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/* Send column address */
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__nand_addr(0);
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if (page_size == 2048)
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__nand_addr(0);
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/* Send page address */
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__nand_addr(page_addr & 0xff);
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__nand_addr((page_addr >> 8) & 0xff);
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if (row_cycle == 3)
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__nand_addr((page_addr >> 16) & 0xff);
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/* Send READSTART command for 2048 ps NAND */
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if (page_size == 2048)
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__nand_cmd(NAND_CMD_READSTART);
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/* Wait for device ready */
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nand_wait_ready();
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/* Read page data */
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data_buf = dst;
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ecc_count = page_size / ECC_BLOCK;
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for (i = 0; i < ecc_count; i++) {
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volatile u8 *paraddr = (volatile u8 *)EMC_NFPAR0;
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unsigned int stat;
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/* Enable RS decoding */
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REG_EMC_NFINTS = 0x0;
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__nand_ecc_rs_decoding();
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/* Read data */
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nand_read_buf((void *)data_buf, ECC_BLOCK, bus_width);
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/* Set PAR values */
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for (j = 0; j < PAR_SIZE; j++) {
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*paraddr++ = oob_buf[ECC_POS + i*PAR_SIZE + j];
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}
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/* Set PRDY */
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REG_EMC_NFECR |= EMC_NFECR_PRDY;
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/* Wait for completion */
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__nand_ecc_decode_sync();
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/* Disable decoding */
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__nand_ecc_disable();
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/* Check result of decoding */
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stat = REG_EMC_NFINTS;
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if (stat & EMC_NFINTS_ERR) {
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/* Error occurred */
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if (stat & EMC_NFINTS_UNCOR) {
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/* Uncorrectable error occurred */
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}
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else {
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unsigned int errcnt, index, mask;
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errcnt = (stat & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT;
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switch (errcnt) {
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case 4:
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index = (REG_EMC_NFERR3 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;
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mask = (REG_EMC_NFERR3 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;
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rs_correct(data_buf, index, mask);
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case 3:
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index = (REG_EMC_NFERR2 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;
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mask = (REG_EMC_NFERR2 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;
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rs_correct(data_buf, index, mask);
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case 2:
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index = (REG_EMC_NFERR1 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;
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mask = (REG_EMC_NFERR1 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;
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rs_correct(data_buf, index, mask);
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case 1:
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index = (REG_EMC_NFERR0 & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT;
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mask = (REG_EMC_NFERR0 & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT;
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rs_correct(data_buf, index, mask);
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break;
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default:
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break;
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}
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}
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}
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data_buf += ECC_BLOCK;
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}
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return 0;
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}
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/*
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* Check bad block
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*
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* Note: the bad block flag may be store in either the first or the last
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* page of the block.
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*/
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int block_is_bad(struct nand_param *nandp, int block)
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{
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int page_addr;
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u8 oob_buf[64];
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page_addr = block * nandp->page_per_block;
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nand_read_oob(nandp, page_addr, oob_buf, nandp->oob_size);
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if (oob_buf[nandp->bad_block_pos] != 0xff)
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return 1;
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page_addr = (block + 1) * nandp->page_per_block - 1;
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nand_read_oob(nandp, page_addr, oob_buf, nandp->oob_size);
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if (oob_buf[nandp->bad_block_pos] != 0xff)
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return 1;
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return 0;
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}
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/*
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* Enable NAND controller
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*/
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void nand_enable(void)
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{
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__nand_enable();
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REG_EMC_SMCR1 = 0x04444400;
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}
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/*
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* Disable NAND controller
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*/
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void nand_disable(void)
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{
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__nand_disable();
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}
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#endif /* CONFIG_JZ4740 */
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