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xburst-tools/qiboot/include/s3c6410.h
Andy Green f18c42310f qi-clean-s3c6410.h-add-uart3.patch 
Signed-off-by: Andy Green <andy@openmoko.com>
2008-11-28 10:16:44 +00:00

1393 lines
53 KiB
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/*
* (C) Copyright 2007
* Byungjae Lee, Samsung Erectronics, bjlee@samsung.com.
* - only support for S3C6400
* $Id: s3c6410.h,v 1.6 2008/07/02 11:01:48 jsgood Exp $
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/************************************************
* NAME : s3c6400.h
*
* Based on S3C6400 User's manual Rev 0.0
************************************************/
#ifndef __S3C6410_H__
#define __S3C6410_H__
#ifndef CONFIG_S3C6410
#define CONFIG_S3C6410 1
#endif
#define S3C64XX_UART_CHANNELS 4
#define S3C64XX_SPI_CHANNELS 2
#define HSMMC_CHANNEL 0
#define MOVI_INIT_REQUIRED 0
#define TCM_BASE 0x0C004000
#define BL2_BASE 0x57E00000
#define CopyMovitoMem(a,b,c,d,e) (((int(*)(int, uint, ushort, uint *, int))(*((uint *)(TCM_BASE + 0x8))))(a,b,c,d,e))
#define SS_SIZE (8 * 1024)
#define eFUSE_SIZE (1 * 1024) // 0.5k eFuse, 0.5k reserved`
#define PART_UBOOT_OFFSET 0x0
#define PART_ZIMAGE_OFFSET 0x40000
#define PART_ROOTFS_OFFSET 0x200000
#define PART_EXTRA_OFFSET 0x3200000
/* movinand definitions */
#define MOVI_BLKSIZE 512
#define MOVI_TOTAL_BLKCNT 7864320 // 7864320 // 3995648 // 1003520 /* static movinand total block count: for writing to movinand when nand boot */
#define MOVI_HIGH_CAPACITY 0
#define MOVI_LAST_BLKPOS (MOVI_TOTAL_BLKCNT - (eFUSE_SIZE / MOVI_BLKSIZE))
#define MOVI_BL1_BLKCNT (SS_SIZE / MOVI_BLKSIZE)
#define MOVI_ENV_BLKCNT (CFG_ENV_SIZE / MOVI_BLKSIZE)
#define MOVI_BL2_BLKCNT (((PART_ZIMAGE_OFFSET - PART_UBOOT_OFFSET) / MOVI_BLKSIZE) - MOVI_ENV_BLKCNT)
#define MOVI_ZIMAGE_BLKCNT ((PART_ROOTFS_OFFSET - PART_ZIMAGE_OFFSET) / MOVI_BLKSIZE)
#define MOVI_BL2_POS (MOVI_LAST_BLKPOS - MOVI_BL1_BLKCNT - MOVI_BL2_BLKCNT - MOVI_ENV_BLKCNT)
#ifndef __ASSEMBLY__
struct movi_offset_t {
uint last;
uint bl1;
uint env;
uint bl2;
uint zimage;
};
/* external functions */
extern void hsmmc_set_gpio(void);
extern void hsmmc_reset (void);
extern int hsmmc_init (void);
extern void test_hsmmc (uint width, uint test, uint start_blk, uint blknum);
typedef enum {
S3C64XX_UART0,
S3C64XX_UART1,
S3C64XX_UART2,
S3C64XX_UART3,
} S3C64XX_UARTS_NR;
#define __REG(x) (*((volatile unsigned int *)(x)))
//#include <s3c64x0.h>
#endif
#define BIT0 0x00000001
#define BIT1 0x00000002
#define BIT2 0x00000004
#define BIT3 0x00000008
#define BIT4 0x00000010
#define BIT5 0x00000020
#define BIT6 0x00000040
#define BIT7 0x00000080
#define BIT8 0x00000100
#define BIT9 0x00000200
#define BIT10 0x00000400
#define BIT11 0x00000800
#define BIT12 0x00001000
#define BIT13 0x00002000
#define BIT14 0x00004000
#define BIT15 0x00008000
#define BIT16 0x00010000
#define BIT17 0x00020000
#define BIT18 0x00040000
#define BIT19 0x00080000
#define BIT20 0x00100000
#define BIT21 0x00200000
#define BIT22 0x00400000
#define BIT23 0x00800000
#define BIT24 0x01000000
#define BIT25 0x02000000
#define BIT26 0x04000000
#define BIT27 0x08000000
#define BIT28 0x10000000
#define BIT29 0x20000000
#define BIT30 0x40000000
#define BIT31 0x80000000
#define ROM_BASE0 0x00000000 /* base address of rom bank 0 */
#define ROM_BASE1 0x04000000 /* base address of rom bank 1 */
#define DRAM_BASE0 0x40000000 /* base address of dram bank 0 */
#define DRAM_BASE1 0x50000000 /* base address of dram bank 1 */
/* S3C6400 device base addresses */
#define ELFIN_DMA_BASE 0x75000000
#define ELFIN_LCD_BASE 0x77100000
#define ELFIN_USB_HOST_BASE 0x74300000
#define ELFIN_I2C_BASE 0x7f004000
#define ELFIN_I2S_BASE 0x7f002000
#define ELFIN_ADC_BASE 0x7e00b000
#define ELFIN_SPI_BASE 0x7f00b000
#define ELFIN_HSMMC_0_BASE 0x7c200000
#define ELFIN_HSMMC_1_BASE 0x7c300000
#define ELFIN_HSMMC_2_BASE 0x7c400000
#define ELFIN_CLOCK_POWER_BASE 0x7e00f000
/* Clock & Power Controller for mDirac3*/
#define APLL_LOCK_OFFSET 0x00
#define MPLL_LOCK_OFFSET 0x04
#define EPLL_LOCK_OFFSET 0x08
#define APLL_CON_OFFSET 0x0C
#define MPLL_CON_OFFSET 0x10
#define EPLL_CON0_OFFSET 0x14
#define EPLL_CON1_OFFSET 0x18
#define CLK_SRC_OFFSET 0x1C
#define CLK_DIV0_OFFSET 0x20
#define CLK_DIV1_OFFSET 0x24
#define CLK_DIV2_OFFSET 0x28
#define CLK_OUT_OFFSET 0x2C
#define HCLK_GATE_OFFSET 0x30
#define PCLK_GATE_OFFSET 0x34
#define SCLK_GATE_OFFSET 0x38
#define AHB_CON0_OFFSET 0x100
#define AHB_CON1_OFFSET 0x104
#define AHB_CON2_OFFSET 0x108
#define SELECT_DMA_OFFSET 0x110
#define SW_RST_OFFSET 0x114
#define SYS_ID_OFFSET 0x118
#define MEM_SYS_CFG_OFFSET 0x120
#define QOS_OVERRIDE0_OFFSET 0x124
#define QOS_OVERRIDE1_OFFSET 0x128
#define MEM_CFG_STAT_OFFSET 0x12C
#define PWR_CFG_OFFSET 0x804
#define EINT_MASK_OFFSET 0x808
#define NOR_CFG_OFFSET 0x810
#define STOP_CFG_OFFSET 0x814
#define SLEEP_CFG_OFFSET 0x818
#define OSC_FREQ_OFFSET 0x820
#define OSC_STABLE_OFFSET 0x824
#define PWR_STABLE_OFFSET 0x828
#define FPC_STABLE_OFFSET 0x82C
#define MTC_STABLE_OFFSET 0x830
#define OTHERS_OFFSET 0x900
#define RST_STAT_OFFSET 0x904
#define WAKEUP_STAT_OFFSET 0x908
#define BLK_PWR_STAT_OFFSET 0x90C
#define INF_REG0_OFFSET 0xA00
#define INF_REG1_OFFSET 0xA04
#define INF_REG2_OFFSET 0xA08
#define INF_REG3_OFFSET 0xA0C
#define INF_REG4_OFFSET 0xA10
#define INF_REG5_OFFSET 0xA14
#define INF_REG6_OFFSET 0xA18
#define INF_REG7_OFFSET 0xA1C
#define OSC_CNT_VAL_OFFSET 0x824
#define PWR_CNT_VAL_OFFSET 0x828
#define FPC_CNT_VAL_OFFSET 0x82C
#define MTC_CNT_VAL_OFFSET 0x830
#define APLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE+APLL_LOCK_OFFSET)
#define MPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE+MPLL_LOCK_OFFSET)
#define EPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE+EPLL_LOCK_OFFSET)
#define APLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE+APLL_CON_OFFSET)
#define MPLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE+MPLL_CON_OFFSET)
#define EPLL_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE+EPLL_CON0_OFFSET)
#define EPLL_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE+EPLL_CON1_OFFSET)
#define CLK_SRC_REG __REG(ELFIN_CLOCK_POWER_BASE+CLK_SRC_OFFSET)
#define CLK_DIV0_REG __REG(ELFIN_CLOCK_POWER_BASE+CLK_DIV0_OFFSET)
#define CLK_DIV1_REG __REG(ELFIN_CLOCK_POWER_BASE+CLK_DIV1_OFFSET)
#define CLK_DIV2_REG __REG(ELFIN_CLOCK_POWER_BASE+CLK_DIV2_OFFSET)
#define CLK_OUT_REG __REG(ELFIN_CLOCK_POWER_BASE+CLK_OUT_OFFSET)
#define HCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE+HCLK_GATE_OFFSET)
#define PCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE+PCLK_GATE_OFFSET)
#define SCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE+SCLK_GATE_OFFSET)
#define AHB_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE+AHB_CON0_OFFSET)
#define AHB_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE+AHB_CON1_OFFSET)
#define AHB_CON2_REG __REG(ELFIN_CLOCK_POWER_BASE+AHB_CON2_OFFSET)
#define SELECT_DMA_REG __REG(ELFIN_CLOCK_POWER_BASE+SELECT_DMA_OFFSET)
#define SW_RST_REG __REG(ELFIN_CLOCK_POWER_BASE+SW_RST_OFFSET)
#define SYS_ID_REG __REG(ELFIN_CLOCK_POWER_BASE+SYS_ID_OFFSET)
#define MEM_SYS_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE+MEM_SYS_CFG_OFFSET)
#define QOS_OVERRIDE0_REG __REG(ELFIN_CLOCK_POWER_BASE+QOS_OVERRIDE0_OFFSET)
#define QOS_OVERRIDE1_REG __REG(ELFIN_CLOCK_POWER_BASE+QOS_OVERRIDE1_OFFSET)
#define MEM_CFG_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE+MEM_CFG_STAT_OFFSET)
#define PWR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE+PWR_CFG_OFFSET)
#define EINT_MASK_REG __REG(ELFIN_CLOCK_POWER_BASE+EINT_MASK_OFFSET)
#define NOR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE+NOR_CFG_OFFSET)
#define STOP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE+STOP_CFG_OFFSET)
#define SLEEP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE+SLEEP_CFG_OFFSET)
#define OSC_FREQ_REG __REG(ELFIN_CLOCK_POWER_BASE+OSC_FREQ_OFFSET)
#define OSC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE+OSC_CNT_VAL_OFFSET)
#define PWR_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE+PWR_CNT_VAL_OFFSET)
#define FPC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE+FPC_CNT_VAL_OFFSET)
#define MTC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE+MTC_CNT_VAL_OFFSET)
#define OTHERS_REG __REG(ELFIN_CLOCK_POWER_BASE+OTHERS_OFFSET)
#define RST_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE+RST_STAT_OFFSET)
#define WAKEUP_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE+WAKEUP_STAT_OFFSET)
#define BLK_PWR_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE+BLK_PWR_STAT_OFFSET)
#define INF_REG0_REG __REG(ELFIN_CLOCK_POWER_BASE+INF_REG0_OFFSET)
#define INF_REG1_REG __REG(ELFIN_CLOCK_POWER_BASE+INF_REG1_OFFSET)
#define INF_REG2_REG __REG(ELFIN_CLOCK_POWER_BASE+INF_REG2_OFFSET)
#define INF_REG3_REG __REG(ELFIN_CLOCK_POWER_BASE+INF_REG3_OFFSET)
#define INF_REG4_REG __REG(ELFIN_CLOCK_POWER_BASE+INF_REG4_OFFSET)
#define INF_REG5_REG __REG(ELFIN_CLOCK_POWER_BASE+INF_REG5_OFFSET)
#define INF_REG6_REG __REG(ELFIN_CLOCK_POWER_BASE+INF_REG6_OFFSET)
#define INF_REG7_REG __REG(ELFIN_CLOCK_POWER_BASE+INF_REG7_OFFSET)
#define APLL_LOCK (ELFIN_CLOCK_POWER_BASE+APLL_LOCK_OFFSET)
#define MPLL_LOCK (ELFIN_CLOCK_POWER_BASE+MPLL_LOCK_OFFSET)
#define EPLL_LOCK (ELFIN_CLOCK_POWER_BASE+EPLL_LOCK_OFFSET)
#define APLL_CON (ELFIN_CLOCK_POWER_BASE+APLL_CON_OFFSET)
#define MPLL_CON (ELFIN_CLOCK_POWER_BASE+MPLL_CON_OFFSET)
#define EPLL_CON0 (ELFIN_CLOCK_POWER_BASE+EPLL_CON0_OFFSET)
#define EPLL_CON1 (ELFIN_CLOCK_POWER_BASE+EPLL_CON1_OFFSET)
#define CLK_SRC (ELFIN_CLOCK_POWER_BASE+CLK_SRC_OFFSET)
#define CLK_DIV0 (ELFIN_CLOCK_POWER_BASE+CLK_DIV0_OFFSET)
#define CLK_DIV1 (ELFIN_CLOCK_POWER_BASE+CLK_DIV1_OFFSET)
#define CLK_DIV2 (ELFIN_CLOCK_POWER_BASE+CLK_DIV2_OFFSET)
#define CLK_OUT (ELFIN_CLOCK_POWER_BASE+CLK_OUT_OFFSET)
#define HCLK_GATE (ELFIN_CLOCK_POWER_BASE+HCLK_GATE_OFFSET)
#define PCLK_GATE (ELFIN_CLOCK_POWER_BASE+PCLK_GATE_OFFSET)
#define SCLK_GATE (ELFIN_CLOCK_POWER_BASE+SCLK_GATE_OFFSET)
#define AHB_CON0 (ELFIN_CLOCK_POWER_BASE+AHB_CON0_OFFSET)
#define AHB_CON1 (ELFIN_CLOCK_POWER_BASE+AHB_CON1_OFFSET)
#define AHB_CON2 (ELFIN_CLOCK_POWER_BASE+AHB_CON2_OFFSET)
#define SELECT_DMA (ELFIN_CLOCK_POWER_BASE+SELECT_DMA_OFFSET)
#define SW_RST (ELFIN_CLOCK_POWER_BASE+SW_RST_OFFSET)
#define SYS_ID (ELFIN_CLOCK_POWER_BASE+SYS_ID_OFFSET)
#define MEM_SYS_CFG (ELFIN_CLOCK_POWER_BASE+MEM_SYS_CFG_OFFSET)
#define QOS_OVERRIDE0 (ELFIN_CLOCK_POWER_BASE+QOS_OVERRIDE0_OFFSET)
#define QOS_OVERRIDE1 (ELFIN_CLOCK_POWER_BASE+QOS_OVERRIDE1_OFFSET)
#define MEM_CFG_STAT (ELFIN_CLOCK_POWER_BASE+MEM_CFG_STAT_OFFSET)
#define PWR_CFG (ELFIN_CLOCK_POWER_BASE+PWR_CFG_OFFSET)
#define EINT_MASK (ELFIN_CLOCK_POWER_BASE+EINT_MASK_OFFSET)
#define NOR_CFG (ELFIN_CLOCK_POWER_BASE+NOR_CFG_OFFSET)
#define STOP_CFG (ELFIN_CLOCK_POWER_BASE+STOP_CFG_OFFSET)
#define SLEEP_CFG (ELFIN_CLOCK_POWER_BASE+SLEEP_CFG_OFFSET)
#define OSC_FREQ (ELFIN_CLOCK_POWER_BASE+OSC_FREQ_OFFSET)
#define OSC_CNT_VAL (ELFIN_CLOCK_POWER_BASE+OSC_CNT_VAL_OFFSET)
#define PWR_CNT_VAL (ELFIN_CLOCK_POWER_BASE+PWR_CNT_VAL_OFFSET)
#define FPC_CNT_VAL (ELFIN_CLOCK_POWER_BASE+FPC_CNT_VAL_OFFSET)
#define MTC_CNT_VAL (ELFIN_CLOCK_POWER_BASE+MTC_CNT_VAL_OFFSET)
#define OTHERS (ELFIN_CLOCK_POWER_BASE+OTHERS_OFFSET)
#define RST_STAT (ELFIN_CLOCK_POWER_BASE+RST_STAT_OFFSET)
#define WAKEUP_STAT (ELFIN_CLOCK_POWER_BASE+WAKEUP_STAT_OFFSET)
#define BLK_PWR_STAT (ELFIN_CLOCK_POWER_BASE+BLK_PWR_STAT_OFFSET)
#define INF_REG0 (ELFIN_CLOCK_POWER_BASE+INF_REG0_OFFSET)
#define INF_REG1 (ELFIN_CLOCK_POWER_BASE+INF_REG1_OFFSET)
#define INF_REG2 (ELFIN_CLOCK_POWER_BASE+INF_REG2_OFFSET)
#define INF_REG3 (ELFIN_CLOCK_POWER_BASE+INF_REG3_OFFSET)
#define INF_REG4 (ELFIN_CLOCK_POWER_BASE+INF_REG4_OFFSET)
#define INF_REG5 (ELFIN_CLOCK_POWER_BASE+INF_REG5_OFFSET)
#define INF_REG6 (ELFIN_CLOCK_POWER_BASE+INF_REG6_OFFSET)
#define INF_REG7 (ELFIN_CLOCK_POWER_BASE+INF_REG7_OFFSET)
/*
* GPIO
*/
#define ELFIN_GPIO_BASE 0x7f008000
#define GPACON_OFFSET 0x00
#define GPADAT_OFFSET 0x04
#define GPAPUD_OFFSET 0x08
#define GPACONSLP_OFFSET 0x0C
#define GPAPUDSLP_OFFSET 0x10
#define GPBCON_OFFSET 0x20
#define GPBDAT_OFFSET 0x24
#define GPBPUD_OFFSET 0x28
#define GPBCONSLP_OFFSET 0x2C
#define GPBPUDSLP_OFFSET 0x30
#define GPCCON_OFFSET 0x40
#define GPCDAT_OFFSET 0x44
#define GPCPUD_OFFSET 0x48
#define GPCCONSLP_OFFSET 0x4C
#define GPCPUDSLP_OFFSET 0x50
#define GPDCON_OFFSET 0x60
#define GPDDAT_OFFSET 0x64
#define GPDPUD_OFFSET 0x68
#define GPDCONSLP_OFFSET 0x6C
#define GPDPUDSLP_OFFSET 0x70
#define GPECON_OFFSET 0x80
#define GPEDAT_OFFSET 0x84
#define GPEPUD_OFFSET 0x88
#define GPECONSLP_OFFSET 0x8C
#define GPEPUDSLP_OFFSET 0x90
#define GPFCON_OFFSET 0xA0
#define GPFDAT_OFFSET 0xA4
#define GPFPUD_OFFSET 0xA8
#define GPFCONSLP_OFFSET 0xAC
#define GPFPUDSLP_OFFSET 0xB0
#define GPGCON_OFFSET 0xC0
#define GPGDAT_OFFSET 0xC4
#define GPGPUD_OFFSET 0xC8
#define GPGCONSLP_OFFSET 0xCC
#define GPGPUDSLP_OFFSET 0xD0
#define GPHCON0_OFFSET 0xE0
#define GPHCON1_OFFSET 0xE4
#define GPHDAT_OFFSET 0xE8
#define GPHPUD_OFFSET 0xEC
#define GPHCONSLP_OFFSET 0xF0
#define GPHPUDSLP_OFFSET 0xF4
#define GPICON_OFFSET 0x100
#define GPIDAT_OFFSET 0x104
#define GPIPUD_OFFSET 0x108
#define GPICONSLP_OFFSET 0x10C
#define GPIPUDSLP_OFFSET 0x110
#define GPJCON_OFFSET 0x120
#define GPJDAT_OFFSET 0x124
#define GPJPUD_OFFSET 0x128
#define GPJCONSLP_OFFSET 0x12C
#define GPJPUDSLP_OFFSET 0x130
#define SPCON_OFFSET 0x1A0
#define MEM0DRVCON_OFFSET 0x1D0
#define MEM1DRVCON_OFFSET 0x1D4
#define GPKCON0_OFFSET 0x800
#define GPKCON1_OFFSET 0x804
#define GPKDAT_OFFSET 0x808
#define GPKPUD_OFFSET 0x80C
#define GPLCON0_OFFSET 0x810
#define GPLCON1_OFFSET 0x814
#define GPLDAT_OFFSET 0x818
#define GPLPUD_OFFSET 0x81C
#define GPMCON_OFFSET 0x820
#define GPMDAT_OFFSET 0x824
#define GPMPUD_OFFSET 0x828
#define GPNCON_OFFSET 0x830
#define GPNDAT_OFFSET 0x834
#define GPNPUD_OFFSET 0x838
#define GPOCON_OFFSET 0x140
#define GPODAT_OFFSET 0x144
#define GPOPUD_OFFSET 0x148
#define GPOCONSLP_OFFSET 0x14C
#define GPOPUDSLP_OFFSET 0x150
#define GPPCON_OFFSET 0x160
#define GPPDAT_OFFSET 0x164
#define GPPPUD_OFFSET 0x168
#define GPPCONSLP_OFFSET 0x16C
#define GPPPUDSLP_OFFSET 0x170
#define GPQCON_OFFSET 0x180
#define GPQDAT_OFFSET 0x184
#define GPQPUD_OFFSET 0x188
#define GPQCONSLP_OFFSET 0x18C
#define GPQPUDSLP_OFFSET 0x190
#define EINTPEND_OFFSET 0x924
#define GPACON_REG __REG(ELFIN_GPIO_BASE+GPACON_OFFSET)
#define GPADAT_REG __REG(ELFIN_GPIO_BASE+GPADAT_OFFSET)
#define GPAPUD_REG __REG(ELFIN_GPIO_BASE+GPAPUD_OFFSET)
#define GPACONSLP_REG __REG(ELFIN_GPIO_BASE+GPACONSLP_OFFSET)
#define GPAPUDSLP_REG __REG(ELFIN_GPIO_BASE+GPAPUDSLP_OFFSET)
#define GPBCON_REG __REG(ELFIN_GPIO_BASE+GPBCON_OFFSET)
#define GPBDAT_REG __REG(ELFIN_GPIO_BASE+GPBDAT_OFFSET)
#define GPBPUD_REG __REG(ELFIN_GPIO_BASE+GPBPUD_OFFSET)
#define GPBCONSLP_REG __REG(ELFIN_GPIO_BASE+GPBCONSLP_OFFSET)
#define GPBPUDSLP_REG __REG(ELFIN_GPIO_BASE+GPBPUDSLP_OFFSET)
#define GPCCON_REG __REG(ELFIN_GPIO_BASE+GPCCON_OFFSET)
#define GPCDAT_REG __REG(ELFIN_GPIO_BASE+GPCDAT_OFFSET)
#define GPCPUD_REG __REG(ELFIN_GPIO_BASE+GPCPUD_OFFSET)
#define GPCCONSLP_REG __REG(ELFIN_GPIO_BASE+GPCCONSLP_OFFSET)
#define GPCPUDSLP_REG __REG(ELFIN_GPIO_BASE+GPCPUDSLP_OFFSET)
#define GPDCON_REG __REG(ELFIN_GPIO_BASE+GPDCON_OFFSET)
#define GPDDAT_REG __REG(ELFIN_GPIO_BASE+GPDDAT_OFFSET)
#define GPDPUD_REG __REG(ELFIN_GPIO_BASE+GPDPUD_OFFSET)
#define GPDCONSLP_REG __REG(ELFIN_GPIO_BASE+GPDCONSLP_OFFSET)
#define GPDPUDSLP_REG __REG(ELFIN_GPIO_BASE+GPDPUDSLP_OFFSET)
#define GPECON_REG __REG(ELFIN_GPIO_BASE+GPECON_OFFSET)
#define GPEDAT_REG __REG(ELFIN_GPIO_BASE+GPEDAT_OFFSET)
#define GPEPUD_REG __REG(ELFIN_GPIO_BASE+GPEPUD_OFFSET)
#define GPECONSLP_REG __REG(ELFIN_GPIO_BASE+GPECONSLP_OFFSET)
#define GPEPUDSLP_REG __REG(ELFIN_GPIO_BASE+GPEPUDSLP_OFFSET)
#define GPFCON_REG __REG(ELFIN_GPIO_BASE+GPFCON_OFFSET)
#define GPFDAT_REG __REG(ELFIN_GPIO_BASE+GPFDAT_OFFSET)
#define GPFPUD_REG __REG(ELFIN_GPIO_BASE+GPFPUD_OFFSET)
#define GPFCONSLP_REG __REG(ELFIN_GPIO_BASE+GPFCONSLP_OFFSET)
#define GPFPUDSLP_REG __REG(ELFIN_GPIO_BASE+GPFPUDSLP_OFFSET)
#define GPGCON_REG __REG(ELFIN_GPIO_BASE+GPGCON_OFFSET)
#define GPGDAT_REG __REG(ELFIN_GPIO_BASE+GPGDAT_OFFSET)
#define GPGPUD_REG __REG(ELFIN_GPIO_BASE+GPGPUD_OFFSET)
#define GPGCONSLP_REG __REG(ELFIN_GPIO_BASE+GPGCONSLP_OFFSET)
#define GPGPUDSLP_REG __REG(ELFIN_GPIO_BASE+GPGPUDSLP_OFFSET)
#define GPHCON0_REG __REG(ELFIN_GPIO_BASE+GPHCON0_OFFSET)
#define GPHCON1_REG __REG(ELFIN_GPIO_BASE+GPHCON1_OFFSET)
#define GPHDAT_REG __REG(ELFIN_GPIO_BASE+GPHDAT_OFFSET)
#define GPHPUD_REG __REG(ELFIN_GPIO_BASE+GPHPUD_OFFSET)
#define GPHCONSLP_REG __REG(ELFIN_GPIO_BASE+GPHCONSLP_OFFSET)
#define GPHPUDSLP_REG __REG(ELFIN_GPIO_BASE+GPHPUDSLP_OFFSET)
#define GPICON_REG __REG(ELFIN_GPIO_BASE+GPICON_OFFSET)
#define GPIDAT_REG __REG(ELFIN_GPIO_BASE+GPIDAT_OFFSET)
#define GPIPUD_REG __REG(ELFIN_GPIO_BASE+GPIPUD_OFFSET)
#define GPICONSLP_REG __REG(ELFIN_GPIO_BASE+GPICONSLP_OFFSET)
#define GPIPUDSLP_REG __REG(ELFIN_GPIO_BASE+GPIPUDSLP_OFFSET)
#define GPJCON_REG __REG(ELFIN_GPIO_BASE+GPJCON_OFFSET)
#define GPJDAT_REG __REG(ELFIN_GPIO_BASE+GPJDAT_OFFSET)
#define GPJPUD_REG __REG(ELFIN_GPIO_BASE+GPJPUD_OFFSET)
#define GPJCONSLP_REG __REG(ELFIN_GPIO_BASE+GPJCONSLP_OFFSET)
#define GPJPUDSLP_REG __REG(ELFIN_GPIO_BASE+GPJPUDSLP_OFFSET)
#define GPKCON0_REG __REG(ELFIN_GPIO_BASE+GPKCON0_OFFSET)
#define GPKCON1_REG __REG(ELFIN_GPIO_BASE+GPKCON1_OFFSET)
#define GPKDAT_REG __REG(ELFIN_GPIO_BASE+GPKDAT_OFFSET)
#define GPKPUD_REG __REG(ELFIN_GPIO_BASE+GPKPUD_OFFSET)
#define GPLCON0_REG __REG(ELFIN_GPIO_BASE+GPLCON0_OFFSET)
#define GPLCON1_REG __REG(ELFIN_GPIO_BASE+GPLCON1_OFFSET)
#define GPLDAT_REG __REG(ELFIN_GPIO_BASE+GPLDAT_OFFSET)
#define GPLPUD_REG __REG(ELFIN_GPIO_BASE+GPLPUD_OFFSET)
#define GPMCON_REG __REG(ELFIN_GPIO_BASE+GPMCON_OFFSET)
#define GPMDAT_REG __REG(ELFIN_GPIO_BASE+GPMDAT_OFFSET)
#define GPMPUD_REG __REG(ELFIN_GPIO_BASE+GPMPUD_OFFSET)
#define GPNCON_REG __REG(ELFIN_GPIO_BASE+GPNCON_OFFSET)
#define GPNDAT_REG __REG(ELFIN_GPIO_BASE+GPNDAT_OFFSET)
#define GPNPUD_REG __REG(ELFIN_GPIO_BASE+GPNPUD_OFFSET)
#define GPOCON_REG __REG(ELFIN_GPIO_BASE+GPOCON_OFFSET)
#define GPODAT_REG __REG(ELFIN_GPIO_BASE+GPODAT_OFFSET)
#define GPOPUD_REG __REG(ELFIN_GPIO_BASE+GPOPUD_OFFSET)
#define GPOCONSLP_REG __REG(ELFIN_GPIO_BASE+GPOCONSLP_OFFSET)
#define GPOPUDSLP_REG __REG(ELFIN_GPIO_BASE+GPOPUDSLP_OFFSET)
#define GPPCON_REG __REG(ELFIN_GPIO_BASE+GPPCON_OFFSET)
#define GPPDAT_REG __REG(ELFIN_GPIO_BASE+GPPDAT_OFFSET)
#define GPPPUD_REG __REG(ELFIN_GPIO_BASE+GPPPUD_OFFSET)
#define GPPCONSLP_REG __REG(ELFIN_GPIO_BASE+GPPCONSLP_OFFSET)
#define GPPPUDSLP_REG __REG(ELFIN_GPIO_BASE+GPPPUDSLP_OFFSET)
#define GPQCON_REG __REG(ELFIN_GPIO_BASE+GPQCON_OFFSET)
#define GPQDAT_REG __REG(ELFIN_GPIO_BASE+GPQDAT_OFFSET)
#define GPQPUD_REG __REG(ELFIN_GPIO_BASE+GPQPUD_OFFSET)
#define GPQCONSLP_REG __REG(ELFIN_GPIO_BASE+GPQCONSLP_OFFSET)
#define GPQPUDSLP_REG __REG(ELFIN_GPIO_BASE+GPQPUDSLP_OFFSET)
#define GPACON (ELFIN_GPIO_BASE+GPACON_OFFSET)
#define GPADAT (ELFIN_GPIO_BASE+GPADAT_OFFSET)
#define GPAPUD (ELFIN_GPIO_BASE+GPAPUD_OFFSET)
#define GPACONSLP (ELFIN_GPIO_BASE+GPACONSLP_OFFSET)
#define GPAPUDSLP (ELFIN_GPIO_BASE+GPAPUDSLP_OFFSET)
#define GPBCON (ELFIN_GPIO_BASE+GPBCON_OFFSET)
#define GPBDAT (ELFIN_GPIO_BASE+GPBDAT_OFFSET)
#define GPBPUD (ELFIN_GPIO_BASE+GPBPUD_OFFSET)
#define GPBCONSLP (ELFIN_GPIO_BASE+GPBCONSLP_OFFSET)
#define GPBPUDSLP (ELFIN_GPIO_BASE+GPBPUDSLP_OFFSET)
#define GPCCON (ELFIN_GPIO_BASE+GPCCON_OFFSET)
#define GPCDAT (ELFIN_GPIO_BASE+GPCDAT_OFFSET)
#define GPCPUD (ELFIN_GPIO_BASE+GPCPUD_OFFSET)
#define GPCCONSLP (ELFIN_GPIO_BASE+GPCCONSLP_OFFSET)
#define GPCPUDSLP (ELFIN_GPIO_BASE+GPCPUDSLP_OFFSET)
#define GPDCON (ELFIN_GPIO_BASE+GPDCON_OFFSET)
#define GPDDAT (ELFIN_GPIO_BASE+GPDDAT_OFFSET)
#define GPDPUD (ELFIN_GPIO_BASE+GPDPUD_OFFSET)
#define GPDCONSLP (ELFIN_GPIO_BASE+GPDCONSLP_OFFSET)
#define GPDPUDSLP (ELFIN_GPIO_BASE+GPDPUDSLP_OFFSET)
#define GPECON (ELFIN_GPIO_BASE+GPECON_OFFSET)
#define GPEDAT (ELFIN_GPIO_BASE+GPEDAT_OFFSET)
#define GPEPUD (ELFIN_GPIO_BASE+GPEPUD_OFFSET)
#define GPECONSLP (ELFIN_GPIO_BASE+GPECONSLP_OFFSET)
#define GPEPUDSLP (ELFIN_GPIO_BASE+GPEPUDSLP_OFFSET)
#define GPFCON (ELFIN_GPIO_BASE+GPFCON_OFFSET)
#define GPFDAT (ELFIN_GPIO_BASE+GPFDAT_OFFSET)
#define GPFPUD (ELFIN_GPIO_BASE+GPFPUD_OFFSET)
#define GPFCONSLP (ELFIN_GPIO_BASE+GPFCONSLP_OFFSET)
#define GPFPUDSLP (ELFIN_GPIO_BASE+GPFPUDSLP_OFFSET)
#define GPGCON (ELFIN_GPIO_BASE+GPGCON_OFFSET)
#define GPGDAT (ELFIN_GPIO_BASE+GPGDAT_OFFSET)
#define GPGPUD (ELFIN_GPIO_BASE+GPGPUD_OFFSET)
#define GPGCONSLP (ELFIN_GPIO_BASE+GPGCONSLP_OFFSET)
#define GPGPUDSLP (ELFIN_GPIO_BASE+GPGPUDSLP_OFFSET)
#define GPHCON0 (ELFIN_GPIO_BASE+GPHCON0_OFFSET)
#define GPHCON1 (ELFIN_GPIO_BASE+GPHCON1_OFFSET)
#define GPHDAT (ELFIN_GPIO_BASE+GPHDAT_OFFSET)
#define GPHPUD (ELFIN_GPIO_BASE+GPHPUD_OFFSET)
#define GPHCONSLP (ELFIN_GPIO_BASE+GPHCONSLP_OFFSET)
#define GPHPUDSLP (ELFIN_GPIO_BASE+GPHPUDSLP_OFFSET)
#define GPICON (ELFIN_GPIO_BASE+GPICON_OFFSET)
#define GPIDAT (ELFIN_GPIO_BASE+GPIDAT_OFFSET)
#define GPIPUD (ELFIN_GPIO_BASE+GPIPUD_OFFSET)
#define GPICONSLP (ELFIN_GPIO_BASE+GPICONSLP_OFFSET)
#define GPIPUDSLP (ELFIN_GPIO_BASE+GPIPUDSLP_OFFSET)
#define GPJCON (ELFIN_GPIO_BASE+GPJCON_OFFSET)
#define GPJDAT (ELFIN_GPIO_BASE+GPJDAT_OFFSET)
#define GPJPUD (ELFIN_GPIO_BASE+GPJPUD_OFFSET)
#define GPJCONSLP (ELFIN_GPIO_BASE+GPJCONSLP_OFFSET)
#define GPJPUDSLP (ELFIN_GPIO_BASE+GPJPUDSLP_OFFSET)
#define GPKCON0 (ELFIN_GPIO_BASE+GPKCON0_OFFSET)
#define GPKCON1 (ELFIN_GPIO_BASE+GPKCON1_OFFSET)
#define GPKDAT (ELFIN_GPIO_BASE+GPKDAT_OFFSET)
#define GPKPUD (ELFIN_GPIO_BASE+GPKPUD_OFFSET)
#define GPLCON0 (ELFIN_GPIO_BASE+GPLCON0_OFFSET)
#define GPLCON1 (ELFIN_GPIO_BASE+GPLCON1_OFFSET)
#define GPLDAT (ELFIN_GPIO_BASE+GPLDAT_OFFSET)
#define GPLPUD (ELFIN_GPIO_BASE+GPLPUD_OFFSET)
#define GPMCON (ELFIN_GPIO_BASE+GPMCON_OFFSET)
#define GPMDAT (ELFIN_GPIO_BASE+GPMDAT_OFFSET)
#define GPMPUD (ELFIN_GPIO_BASE+GPMPUD_OFFSET)
#define GPNCON (ELFIN_GPIO_BASE+GPNCON_OFFSET)
#define GPNDAT (ELFIN_GPIO_BASE+GPNDAT_OFFSET)
#define GPNPUD (ELFIN_GPIO_BASE+GPNPUD_OFFSET)
#define GPOCON (ELFIN_GPIO_BASE+GPOCON_OFFSET)
#define GPODAT (ELFIN_GPIO_BASE+GPODAT_OFFSET)
#define GPOPUD (ELFIN_GPIO_BASE+GPOPUD_OFFSET)
#define GPOCONSLP (ELFIN_GPIO_BASE+GPOCONSLP_OFFSET)
#define GPOPUDSLP (ELFIN_GPIO_BASE+GPOPUDSLP_OFFSET)
#define GPPCON (ELFIN_GPIO_BASE+GPPCON_OFFSET)
#define GPPDAT (ELFIN_GPIO_BASE+GPPDAT_OFFSET)
#define GPPPUD (ELFIN_GPIO_BASE+GPPPUD_OFFSET)
#define GPPCONSLP (ELFIN_GPIO_BASE+GPPCONSLP_OFFSET)
#define GPPPUDSLP (ELFIN_GPIO_BASE+GPPPUDSLP_OFFSET)
#define GPQCON (ELFIN_GPIO_BASE+GPQCON_OFFSET)
#define GPQDAT (ELFIN_GPIO_BASE+GPQDAT_OFFSET)
#define GPQPUD (ELFIN_GPIO_BASE+GPQPUD_OFFSET)
#define GPQCONSLP (ELFIN_GPIO_BASE+GPQCONSLP_OFFSET)
#define GPQPUDSLP (ELFIN_GPIO_BASE+GPQPUDSLP_OFFSET)
/*
* Bus Matrix
*/
#define ELFIN_MEM_SYS_CFG 0x7e00f120
/*
* Memory controller
*/
#define ELFIN_SROM_BASE 0x70000000
#define SROM_BW_REG __REG(ELFIN_SROM_BASE+0x0)
#define SROM_BC0_REG __REG(ELFIN_SROM_BASE+0x4)
#define SROM_BC1_REG __REG(ELFIN_SROM_BASE+0x8)
#define SROM_BC2_REG __REG(ELFIN_SROM_BASE+0xC)
#define SROM_BC3_REG __REG(ELFIN_SROM_BASE+0x10)
#define SROM_BC4_REG __REG(ELFIN_SROM_BASE+0x14)
#define SROM_BC5_REG __REG(ELFIN_SROM_BASE+0x18)
/*
* SDRAM Controller
*/
#define ELFIN_DMC0_BASE 0x7e000000
#define ELFIN_DMC1_BASE 0x7e001000
#define INDEX_DMC_MEMC_STATUS (0x00)
#define INDEX_DMC_MEMC_CMD (0x04)
#define INDEX_DMC_DIRECT_CMD (0x08)
#define INDEX_DMC_MEMORY_CFG (0x0C)
#define INDEX_DMC_REFRESH_PRD (0x10)
#define INDEX_DMC_CAS_LATENCY (0x14)
#define INDEX_DMC_T_DQSS (0x18)
#define INDEX_DMC_T_MRD (0x1C)
#define INDEX_DMC_T_RAS (0x20)
#define INDEX_DMC_T_RC (0x24)
#define INDEX_DMC_T_RCD (0x28)
#define INDEX_DMC_T_RFC (0x2C)
#define INDEX_DMC_T_RP (0x30)
#define INDEX_DMC_T_RRD (0x34)
#define INDEX_DMC_T_WR (0x38)
#define INDEX_DMC_T_WTR (0x3C)
#define INDEX_DMC_T_XP (0x40)
#define INDEX_DMC_T_XSR (0x44)
#define INDEX_DMC_T_ESR (0x48)
#define INDEX_DMC_MEMORY_CFG2 (0x4C)
#define INDEX_DMC_CHIP_0_CFG (0x200)
#define INDEX_DMC_CHIP_1_CFG (0x204)
#define INDEX_DMC_CHIP_2_CFG (0x208)
#define INDEX_DMC_CHIP_3_CFG (0x20C)
#define INDEX_DMC_USER_STATUS (0x300)
#define INDEX_DMC_USER_CONFIG (0x304)
/*
* Memory Chip direct command
*/
#define DMC_NOP0 0x0c0000
#define DMC_NOP1 0x1c0000
#define DMC_PA0 0x000000 //Precharge all
#define DMC_PA1 0x100000
#define DMC_AR0 0x040000 //Autorefresh
#define DMC_AR1 0x140000
#define DMC_SDR_MR0 0x080032 //MRS, CAS 3, Burst Length 4
#define DMC_SDR_MR1 0x180032
#define DMC_DDR_MR0 0x080162
#define DMC_DDR_MR1 0x180162
#define DMC_mDDR_MR0 0x080032 //CAS 3, Burst Length 4
#define DMC_mDDR_MR1 0x180032
#define DMC_mSDR_EMR0 0x0a0000 //EMRS, DS:Full, PASR:Full Array
#define DMC_mSDR_EMR1 0x1a0000
#define DMC_DDR_EMR0 0x090000
#define DMC_DDR_EMR1 0x190000
#define DMC_mDDR_EMR0 0x0a0000 // DS:Full, PASR:Full Array
#define DMC_mDDR_EMR1 0x1a0000
/****************************************************************
Definitions for memory configuration
Set memory configuration
active_chips = 1'b0 (1 chip)
qos_master_chip = 3'b000(ARID[3:0])
memory burst = 3'b010(burst 4)
stop_mem_clock = 1'b0(disable dynamical stop)
auto_power_down = 1'b0(disable auto power-down mode)
power_down_prd = 6'b00_0000(0 cycle for auto power-down)
ap_bit = 1'b0 (bit position of auto-precharge is 10)
row_bits = 3'b010(# row address 13)
column_bits = 3'b010(# column address 10 )
Set user configuration
2'b10=SDRAM/mSDRAM, 2'b11=DDR, 2'b01=mDDR
Set chip select for chip [n]
row bank control, bank address 0x3000_0000 ~ 0x37ff_ffff
CHIP_[n]_CFG=0x30F8, 30: ADDR[31:24], F8: Mask[31:24]
******************************************************************/
/*
* HS MMC Interface
*/
#define ELFIN_HSMMC_BASE 0x7C200000
#define HM_SYSAD (0x00)
#define HM_BLKSIZE (0x04)
#define HM_BLKCNT (0x06)
#define HM_ARGUMENT (0x08)
#define HM_TRNMOD (0x0c)
#define HM_CMDREG (0x0e)
#define HM_RSPREG0 (0x10)
#define HM_RSPREG1 (0x14)
#define HM_RSPREG2 (0x18)
#define HM_RSPREG3 (0x1c)
#define HM_BDATA (0x20)
#define HM_PRNSTS (0x24)
#define HM_HOSTCTL (0x28)
#define HM_PWRCON (0x29)
#define HM_BLKGAP (0x2a)
#define HM_WAKCON (0x2b)
#define HM_CLKCON (0x2c)
#define HM_TIMEOUTCON (0x2e)
#define HM_SWRST (0x2f)
#define HM_NORINTSTS (0x30)
#define HM_ERRINTSTS (0x32)
#define HM_NORINTSTSEN (0x34)
#define HM_ERRINTSTSEN (0x36)
#define HM_NORINTSIGEN (0x38)
#define HM_ERRINTSIGEN (0x3a)
#define HM_ACMD12ERRSTS (0x3c)
#define HM_CAPAREG (0x40)
#define HM_MAXCURR (0x48)
#define HM_CONTROL2 (0x80)
#define HM_CONTROL3 (0x84)
#define HM_CONTROL4 (0x8c)
#define HM_HCVER (0xfe)
/*
* Nand flash controller
*/
#define ELFIN_NAND_BASE 0x70200000
#define NFCONF_OFFSET 0x00
#define NFCONT_OFFSET 0x04
#define NFCMMD_OFFSET 0x08
#define NFADDR_OFFSET 0x0c
#define NFDATA_OFFSET 0x10
#define NFMECCDATA0_OFFSET 0x14
#define NFMECCDATA1_OFFSET 0x18
#define NFSECCDATA0_OFFSET 0x1c
#define NFSBLK_OFFSET 0x20
#define NFEBLK_OFFSET 0x24
#define NFSTAT_OFFSET 0x28
#define NFESTAT0_OFFSET 0x2c
#define NFESTAT1_OFFSET 0x30
#define NFMECC0_OFFSET 0x34
#define NFMECC1_OFFSET 0x38
#define NFSECC_OFFSET 0x3c
#define NFMLCBITPT_OFFSET 0x40
#define NF8ECCERR0_OFFSET 0x44
#define NF8ECCERR1_OFFSET 0x48
#define NF8ECCERR2_OFFSET 0x4c
#define NFM8ECC0_OFFSET 0x50
#define NFM8ECC1_OFFSET 0x54
#define NFM8ECC2_OFFSET 0x58
#define NFM8ECC3_OFFSET 0x5c
#define NFMLC8BITPT0_OFFSET 0x60
#define NFMLC8BITPT1_OFFSET 0x64
#define NFCONF (ELFIN_NAND_BASE+NFCONF_OFFSET)
#define NFCONT (ELFIN_NAND_BASE+NFCONT_OFFSET)
#define NFCMMD (ELFIN_NAND_BASE+NFCMMD_OFFSET)
#define NFADDR (ELFIN_NAND_BASE+NFADDR_OFFSET)
#define NFDATA (ELFIN_NAND_BASE+NFDATA_OFFSET)
#define NFMECCDATA0 (ELFIN_NAND_BASE+NFMECCDATA0_OFFSET)
#define NFMECCDATA1 (ELFIN_NAND_BASE+NFMECCDATA1_OFFSET)
#define NFSECCDATA0 (ELFIN_NAND_BASE+NFSECCDATA0_OFFSET)
#define NFSBLK (ELFIN_NAND_BASE+NFSBLK_OFFSET)
#define NFEBLK (ELFIN_NAND_BASE+NFEBLK_OFFSET)
#define NFSTAT (ELFIN_NAND_BASE+NFSTAT_OFFSET)
#define NFESTAT0 (ELFIN_NAND_BASE+NFESTAT0_OFFSET)
#define NFESTAT1 (ELFIN_NAND_BASE+NFESTAT1_OFFSET)
#define NFMECC0 (ELFIN_NAND_BASE+NFMECC0_OFFSET)
#define NFMECC1 (ELFIN_NAND_BASE+NFMECC1_OFFSET)
#define NFSECC (ELFIN_NAND_BASE+NFSECC_OFFSET)
#define NFMLCBITPT (ELFIN_NAND_BASE+NFMLCBITPT_OFFSET)
#define NF8ECCERR0 (ELFIN_NAND_BASE+NF8ECCERR0_OFFSET)
#define NF8ECCERR1 (ELFIN_NAND_BASE+NF8ECCERR1_OFFSET)
#define NF8ECCERR2 (ELFIN_NAND_BASE+NF8ECCERR2_OFFSET)
#define NFM8ECC0 (ELFIN_NAND_BASE+NFM8ECC0_OFFSET)
#define NFM8ECC1 (ELFIN_NAND_BASE+NFM8ECC1_OFFSET)
#define NFM8ECC2 (ELFIN_NAND_BASE+NFM8ECC2_OFFSET)
#define NFM8ECC3 (ELFIN_NAND_BASE+NFM8ECC3_OFFSET)
#define NFMLC8BITPT0 (ELFIN_NAND_BASE+NFMLC8BITPT0_OFFSET)
#define NFMLC8BITPT1 (ELFIN_NAND_BASE+NFMLC8BITPT1_OFFSET)
#define NFCONF_REG __REG(ELFIN_NAND_BASE+NFCONF_OFFSET)
#define NFCONT_REG __REG(ELFIN_NAND_BASE+NFCONT_OFFSET)
#define NFCMD_REG __REG(ELFIN_NAND_BASE+NFCMMD_OFFSET)
#define NFADDR_REG __REG(ELFIN_NAND_BASE+NFADDR_OFFSET)
#define NFDATA_REG __REG(ELFIN_NAND_BASE+NFDATA_OFFSET)
#define NFDATA8_REG __REGb(ELFIN_NAND_BASE+NFDATA_OFFSET)
#define NFMECCDATA0_REG __REG(ELFIN_NAND_BASE+NFMECCDATA0_OFFSET)
#define NFMECCDATA1_REG __REG(ELFIN_NAND_BASE+NFMECCDATA1_OFFSET)
#define NFSECCDATA0_REG __REG(ELFIN_NAND_BASE+NFSECCDATA0_OFFSET)
#define NFSBLK_REG __REG(ELFIN_NAND_BASE+NFSBLK_OFFSET)
#define NFEBLK_REG __REG(ELFIN_NAND_BASE+NFEBLK_OFFSET)
#define NFSTAT_REG __REG(ELFIN_NAND_BASE+NFSTAT_OFFSET)
#define NFESTAT0_REG __REG(ELFIN_NAND_BASE+NFESTAT0_OFFSET)
#define NFESTAT1_REG __REG(ELFIN_NAND_BASE+NFESTAT1_OFFSET)
#define NFMECC0_REG __REG(ELFIN_NAND_BASE+NFMECC0_OFFSET)
#define NFMECC1_REG __REG(ELFIN_NAND_BASE+NFMECC1_OFFSET)
#define NFSECC_REG __REG(ELFIN_NAND_BASE+NFSECC_OFFSET)
#define NFMLCBITPT_REG __REG(ELFIN_NAND_BASE+NFMLCBITPT_OFFSET)
#define NFCONF_ECC_MLC (1<<24)
#define NFCONT_ECC_ENC (1<<18)
#define NFCONT_WP (1<<16)
#define NFCONT_MECCLOCK (1<<7)
#define NFCONT_SECCLOCK (1<<6)
#define NFCONT_INITMECC (1<<5)
#define NFCONT_INITSECC (1<<4)
#define NFCONT_INITECC (NFCONT_INITMECC | NFCONT_INITSECC)
#define NFCONT_CS_ALT (1<<1)
#define NFCONT_CS (1<<1)
#define NFSTAT_ECCENCDONE (1<<7)
#define NFSTAT_ECCDECDONE (1<<6)
#define NFSTAT_RnB (1<<0)
#define NFESTAT0_ECCBUSY (1<<31)
/*************************************************************
* OneNAND Controller
*************************************************************/
/*
* S3C6400 SFRs
*/
#define ONENAND_REG_MEM_CFG (0x000)
#define ONENAND_REG_BURST_LEN (0x010)
#define ONENAND_REG_MEM_RESET (0x020)
#define ONENAND_REG_INT_ERR_STAT (0x030)
#define ONENAND_REG_INT_ERR_MASK (0x040)
#define ONENAND_REG_INT_ERR_ACK (0x050)
#define ONENAND_REG_ECC_ERR_STAT (0x060)
#define ONENAND_REG_MANUFACT_ID (0x070)
#define ONENAND_REG_DEVICE_ID (0x080)
#define ONENAND_REG_DATA_BUF_SIZE (0x090)
#define ONENAND_REG_BOOT_BUF_SIZE (0x0A0)
#define ONENAND_REG_BUF_AMOUNT (0x0B0)
#define ONENAND_REG_TECH (0x0C0)
#define ONENAND_REG_FBA_WIDTH (0x0D0)
#define ONENAND_REG_FPA_WIDTH (0x0E0)
#define ONENAND_REG_FSA_WIDTH (0x0F0)
#define ONENAND_REG_REVISION (0x100)
#define ONENAND_REG_DATARAM0 (0x110)
#define ONENAND_REG_DATARAM1 (0x120)
#define ONENAND_REG_SYNC_MODE (0x130)
#define ONENAND_REG_TRANS_SPARE (0x140)
#define ONENAND_REG_LOCK_BIT (0x150)
#define ONENAND_REG_DBS_DFS_WIDTH (0x160)
#define ONENAND_REG_PAGE_CNT (0x170)
#define ONENAND_REG_ERR_PAGE_ADDR (0x180)
#define ONENAND_REG_BURST_RD_LAT (0x190)
#define ONENAND_REG_INT_PIN_ENABLE (0x1A0)
#define ONENAND_REG_INT_MON_CYC (0x1B0)
#define ONENAND_REG_ACC_CLOCK (0x1C0)
#define ONENAND_REG_SLOW_RD_PATH (0x1D0)
#define ONENAND_REG_ERR_BLK_ADDR (0x1E0)
#define ONENAND_REG_FLASH_VER_ID (0x1F0)
#define ONENAND_REG_FLASH_AUX_CNTRL (0x300)
/*
* S3C6400 SFR values
*/
#define ONENAND_MEM_CFG_SYNC_READ (1 << 15)
#define ONENAND_MEM_CFG_BRL_7 (7 << 12)
#define ONENAND_MEM_CFG_BRL_6 (6 << 12)
#define ONENAND_MEM_CFG_BRL_5 (5 << 12)
#define ONENAND_MEM_CFG_BRL_4 (4 << 12)
#define ONENAND_MEM_CFG_BRL_3 (3 << 12)
#define ONENAND_MEM_CFG_BRL_10 (2 << 12)
#define ONENAND_MEM_CFG_BRL_9 (1 << 12)
#define ONENAND_MEM_CFG_BRL_8 (0 << 12)
#define ONENAND_MEM_CFG_BRL_SHIFT (12)
#define ONENAND_MEM_CFG_BL_1K (5 << 9)
#define ONENAND_MEM_CFG_BL_32 (4 << 9)
#define ONENAND_MEM_CFG_BL_16 (3 << 9)
#define ONENAND_MEM_CFG_BL_8 (2 << 9)
#define ONENAND_MEM_CFG_BL_4 (1 << 9)
#define ONENAND_MEM_CFG_BL_CONT (0 << 9)
#define ONENAND_MEM_CFG_BL_SHIFT (9)
#define ONENAND_MEM_CFG_NO_ECC (1 << 8)
#define ONENAND_MEM_CFG_RDY_HIGH (1 << 7)
#define ONENAND_MEM_CFG_INT_HIGH (1 << 6)
#define ONENAND_MEM_CFG_IOBE (1 << 5)
#define ONENAND_MEM_CFG_RDY_CONF (1 << 4)
#define ONENAND_MEM_CFG_HF (1 << 2)
#define ONENAND_MEM_CFG_WM_SYNC (1 << 1)
#define ONENAND_MEM_CFG_BWPS_UNLOCK (1 << 0)
#define ONENAND_BURST_LEN_CONT (0)
#define ONENAND_BURST_LEN_4 (4)
#define ONENAND_BURST_LEN_8 (8)
#define ONENAND_BURST_LEN_16 (16)
#define ONENAND_MEM_RESET_WARM (0x1)
#define ONENAND_MEM_RESET_COLD (0x2)
#define ONENAND_MEM_RESET_HOT (0x3)
#define ONENAND_INT_ERR_CACHE_OP_ERR (1 << 13)
#define ONENAND_INT_ERR_RST_CMP (1 << 12)
#define ONENAND_INT_ERR_RDY_ACT (1 << 11)
#define ONENAND_INT_ERR_INT_ACT (1 << 10)
#define ONENAND_INT_ERR_UNSUP_CMD (1 << 9)
#define ONENAND_INT_ERR_LOCKED_BLK (1 << 8)
#define ONENAND_INT_ERR_BLK_RW_CMP (1 << 7)
#define ONENAND_INT_ERR_ERS_CMP (1 << 6)
#define ONENAND_INT_ERR_PGM_CMP (1 << 5)
#define ONENAND_INT_ERR_LOAD_CMP (1 << 4)
#define ONENAND_INT_ERR_ERS_FAIL (1 << 3)
#define ONENAND_INT_ERR_PGM_FAIL (1 << 2)
#define ONENAND_INT_ERR_INT_TO (1 << 1)
#define ONENAND_INT_ERR_LD_FAIL_ECC_ERR (1 << 0)
#define ONENAND_DEVICE_DENSITY_SHIFT (4)
#define ONENAND_DEVICE_IS_DDP (1 << 3)
#define ONENAND_DEVICE_IS_DEMUX (1 << 2)
#define ONENAND_DEVICE_VCC_MASK (0x3)
#define ONENAND_DEVICE_DENSITY_128Mb (0x000)
#define ONENAND_DEVICE_DENSITY_256Mb (0x001)
#define ONENAND_DEVICE_DENSITY_512Mb (0x002)
#define ONENAND_DEVICE_DENSITY_1Gb (0x003)
#define ONENAND_DEVICE_DENSITY_2Gb (0x004)
#define ONENAND_DEVICE_DENSITY_4Gb (0x005)
#define ONENAND_SYNC_MODE_RM_SYNC (1 << 1)
#define ONENAND_SYNC_MODE_WM_SYNC (1 << 0)
#define ONENAND_TRANS_SPARE_TSRF_INC (1 << 0)
#define ONENAND_INT_PIN_ENABLE (1 << 0)
#define ONENAND_ACC_CLOCK_266_133 (0x5)
#define ONENAND_ACC_CLOCK_166_83 (0x3)
#define ONENAND_ACC_CLOCK_134_67 (0x3)
#define ONENAND_ACC_CLOCK_100_50 (0x2)
#define ONENAND_ACC_CLOCK_60_30 (0x2)
#define ONENAND_FLASH_AUX_WD_DISABLE (1 << 0)
/*
* Datain values for mapped commands
*/
#define ONENAND_DATAIN_ERASE_STATUS (0x00)
#define ONENAND_DATAIN_ERASE_MULTI (0x01)
#define ONENAND_DATAIN_ERASE_SINGLE (0x03)
#define ONENAND_DATAIN_ERASE_VERIFY (0x15)
#define ONENAND_DATAIN_UNLOCK_START (0x08)
#define ONENAND_DATAIN_UNLOCK_END (0x09)
#define ONENAND_DATAIN_LOCK_START (0x0A)
#define ONENAND_DATAIN_LOCK_END (0x0B)
#define ONENAND_DATAIN_LOCKTIGHT_START (0x0C)
#define ONENAND_DATAIN_LOCKTIGHT_END (0x0D)
#define ONENAND_DATAIN_UNLOCK_ALL (0x0E)
#define ONENAND_DATAIN_COPYBACK_SRC (0x1000)
#define ONENAND_DATAIN_COPYBACK_DST (0x2000)
#define ONENAND_DATAIN_ACCESS_OTP (0x12)
#define ONENAND_DATAIN_ACCESS_MAIN (0x14)
#define ONENAND_DATAIN_PIPELINE_READ (0x4000)
#define ONENAND_DATAIN_PIPELINE_WRITE (0x4100)
#define ONENAND_DATAIN_RMW_LOAD (0x10)
#define ONENAND_DATAIN_RMW_MODIFY (0x11)
/*
* Device ID Register F001h (R)
*/
#define ONENAND_DEVICE_DENSITY_SHIFT (4)
#define ONENAND_DEVICE_IS_DDP (1 << 3)
#define ONENAND_DEVICE_IS_DEMUX (1 << 2)
#define ONENAND_DEVICE_VCC_MASK (0x3)
/*
* Version ID Register F002h (R)
*/
#define ONENAND_VERSION_PROCESS_SHIFT (8)
/*
* Start Address 1 F100h (R/W)
*/
#define ONENAND_DDP_SHIFT (15)
#define ONENAND_DDP_CHIP0 (0)
#define ONENAND_DDP_CHIP1 (1 << ONENAND_DDP_SHIFT)
/*
* Start Buffer Register F200h (R/W)
*/
#define ONENAND_BSA_MASK (0x03)
#define ONENAND_BSA_SHIFT (8)
#define ONENAND_BSA_BOOTRAM (0 << 2)
#define ONENAND_BSA_DATARAM0 (2 << 2)
#define ONENAND_BSA_DATARAM1 (3 << 2)
#define ONENAND_BSC_MASK (0x03)
/*
* Command Register F220h (R/W)
*/
#define ONENAND_CMD_READ (0x00)
#define ONENAND_CMD_READOOB (0x13)
#define ONENAND_CMD_PROG (0x80)
#define ONENAND_CMD_PROGOOB (0x1A)
#define ONENAND_CMD_UNLOCK (0x23)
#define ONENAND_CMD_LOCK (0x2A)
#define ONENAND_CMD_LOCK_TIGHT (0x2C)
#define ONENAND_CMD_UNLOCK_ALL (0x27)
#define ONENAND_CMD_ERASE (0x94)
#define ONENAND_CMD_RESET (0xF0)
#define ONENAND_CMD_OTP_ACCESS (0x65)
#define ONENAND_CMD_READID (0x90)
#define ONENAND_CMD_STARTADDR1 (0xE0)
#define ONENAND_CMD_WP_STATUS (0xE1)
#define ONENAND_CMD_PIPELINE_READ (0x01)
#define ONENAND_CMD_PIPELINE_WRITE (0x81)
/*
* Command Mapping for S3C6400 OneNAND Controller
*/
#define ONENAND_AHB_ADDR (0x20000000)
#define ONENAND_DUMMY_ADDR (0x20400000)
#define ONENAND_CMD_SHIFT (24)
#define ONENAND_CMD_MAP_00 (0x0)
#define ONENAND_CMD_MAP_01 (0x1)
#define ONENAND_CMD_MAP_10 (0x2)
#define ONENAND_CMD_MAP_11 (0x3)
#define ONENAND_CMD_MAP_FF (0xF)
/*
* Mask for Mapping table
*/
#define ONENAND_MEM_ADDR_MASK (0xffffff)
#define ONENAND_DDP_SHIFT_1Gb (21)
#define ONENAND_DDP_SHIFT_2Gb (22)
#define ONENAND_DDP_SHIFT_4Gb (23)
#define ONENAND_FBA_SHIFT (12)
#define ONENAND_FPA_SHIFT (6)
#define ONENAND_FSA_SHIFT (4)
#define ONENAND_FBA_MASK_128Mb (0xff)
#define ONENAND_FBA_MASK_256Mb (0x1ff)
#define ONENAND_FBA_MASK_512Mb (0x1ff)
#define ONENAND_FBA_MASK_1Gb_DDP (0x1ff)
#define ONENAND_FBA_MASK_1Gb (0x3ff)
#define ONENAND_FBA_MASK_2Gb_DDP (0x3ff)
#define ONENAND_FBA_MASK_2Gb (0x7ff)
#define ONENAND_FBA_MASK_4Gb_DDP (0x7ff)
#define ONENAND_FBA_MASK_4Gb (0xfff)
#define ONENAND_FPA_MASK (0x3f)
#define ONENAND_FSA_MASK (0x3)
/*
* System Configuration 1 Register F221h (R, R/W)
*/
#define ONENAND_SYS_CFG1_SYNC_READ (1 << 15)
#define ONENAND_SYS_CFG1_BRL_7 (7 << 12)
#define ONENAND_SYS_CFG1_BRL_6 (6 << 12)
#define ONENAND_SYS_CFG1_BRL_5 (5 << 12)
#define ONENAND_SYS_CFG1_BRL_4 (4 << 12)
#define ONENAND_SYS_CFG1_BRL_3 (3 << 12)
#define ONENAND_SYS_CFG1_BRL_10 (2 << 12)
#define ONENAND_SYS_CFG1_BRL_9 (1 << 12)
#define ONENAND_SYS_CFG1_BRL_8 (0 << 12)
#define ONENAND_SYS_CFG1_BRL_SHIFT (12)
#define ONENAND_SYS_CFG1_BL_32 (4 << 9)
#define ONENAND_SYS_CFG1_BL_16 (3 << 9)
#define ONENAND_SYS_CFG1_BL_8 (2 << 9)
#define ONENAND_SYS_CFG1_BL_4 (1 << 9)
#define ONENAND_SYS_CFG1_BL_CONT (0 << 9)
#define ONENAND_SYS_CFG1_BL_SHIFT (9)
#define ONENAND_SYS_CFG1_NO_ECC (1 << 8)
#define ONENAND_SYS_CFG1_RDY (1 << 7)
#define ONENAND_SYS_CFG1_INT (1 << 6)
#define ONENAND_SYS_CFG1_IOBE (1 << 5)
#define ONENAND_SYS_CFG1_RDY_CONF (1 << 4)
/*
* Controller Status Register F240h (R)
*/
#define ONENAND_CTRL_ONGO (1 << 15)
#define ONENAND_CTRL_LOCK (1 << 14)
#define ONENAND_CTRL_LOAD (1 << 13)
#define ONENAND_CTRL_PROGRAM (1 << 12)
#define ONENAND_CTRL_ERASE (1 << 11)
#define ONENAND_CTRL_ERROR (1 << 10)
#define ONENAND_CTRL_RSTB (1 << 7)
#define ONENAND_CTRL_OTP_L (1 << 6)
#define ONENAND_CTRL_OTP_BL (1 << 5)
/*
* Interrupt Status Register F241h (R)
*/
#define ONENAND_INT_MASTER (1 << 15)
#define ONENAND_INT_READ (1 << 7)
#define ONENAND_INT_WRITE (1 << 6)
#define ONENAND_INT_ERASE (1 << 5)
#define ONENAND_INT_RESET (1 << 4)
#define ONENAND_INT_CLEAR (0 << 0)
/*
* NAND Flash Write Protection Status Register F24Eh (R)
*/
#define ONENAND_WP_US (1 << 2)
#define ONENAND_WP_LS (1 << 1)
#define ONENAND_WP_LTS (1 << 0)
/*
* ECC Status Register FF00h (R)
*/
#define ONENAND_ECC_1BIT (1 << 0)
#define ONENAND_ECC_1BIT_ALL (0x5555)
#define ONENAND_ECC_2BIT (1 << 1)
#define ONENAND_ECC_2BIT_ALL (0xAAAA)
/*
* One-Time Programmable (OTP)
*/
#define ONENAND_OTP_LOCK_OFFSET (14)
/*************************************************************
* End of OneNAND Controller
*************************************************************/
/*
* Interrupt
*/
#define ELFIN_VIC0_BASE_ADDR (0x71200000)
#define ELFIN_VIC1_BASE_ADDR (0x71300000)
#define oINTMOD (0x0C) // VIC INT SELECT (IRQ or FIQ)
#define oINTUNMSK (0x10) // VIC INT EN (Unmask by writing 1)
#define oINTMSK (0x14) // VIC INT EN CLEAR (Mask by writing 1)
#define oINTSUBMSK (0x1C) // VIC SOFT INT CLEAR
#define oVECTADDR (0xF00) // VIC ADDRESS
/*
* Watchdog timer
*/
#define ELFIN_WATCHDOG_BASE 0x7E004000
#define WTCON_REG __REG(0x7E004004)
#define WTDAT_REG __REG(0x7E004008)
#define WTCNT_REG __REG(0x7E00400C)
/*
* UART
*/
#define ELFIN_UART_BASE 0x7F005000
#define ELFIN_UART0_OFFSET 0x0000
#define ELFIN_UART1_OFFSET 0x0400
#define ELFIN_UART2_OFFSET 0x0800
#define ELFIN_UART3_OFFSET 0x0c00
#define ULCON_OFFSET 0x00
#define UCON_OFFSET 0x04
#define UFCON_OFFSET 0x08
#define UMCON_OFFSET 0x0C
#define UTRSTAT_OFFSET 0x10
#define UERSTAT_OFFSET 0x14
#define UFSTAT_OFFSET 0x18
#define UMSTAT_OFFSET 0x1C
#define UTXH_OFFSET 0x20
#define URXH_OFFSET 0x24
#define UBRDIV_OFFSET 0x28
#define UDIVSLOT_OFFSET 0x2C
#define UINTP_OFFSET 0x30
#define UINTSP_OFFSET 0x34
#define UINTM_OFFSET 0x38
#define ULCON0_REG __REG(0x7F005000)
#define UCON0_REG __REG(0x7F005004)
#define UFCON0_REG __REG(0x7F005008)
#define UMCON0_REG __REG(0x7F00500C)
#define UTRSTAT0_REG __REG(0x7F005010)
#define UERSTAT0_REG __REG(0x7F005014)
#define UFSTAT0_REG __REG(0x7F005018)
#define UMSTAT0_REG __REG(0x7F00501c)
#define UTXH0_REG __REG(0x7F005020)
#define URXH0_REG __REG(0x7F005024)
#define UBRDIV0_REG __REG(0x7F005028)
#define UDIVSLOT0_REG __REG(0x7F00502c)
#define UINTP0_REG __REG(0x7F005030)
#define UINTSP0_REG __REG(0x7F005034)
#define UINTM0_REG __REG(0x7F005038)
#define ULCON1_REG __REG(0x7F005400)
#define UCON1_REG __REG(0x7F005404)
#define UFCON1_REG __REG(0x7F005408)
#define UMCON1_REG __REG(0x7F00540C)
#define UTRSTAT1_REG __REG(0x7F005410)
#define UERSTAT1_REG __REG(0x7F005414)
#define UFSTAT1_REG __REG(0x7F005418)
#define UMSTAT1_REG __REG(0x7F00541c)
#define UTXH1_REG __REG(0x7F005420)
#define URXH1_REG __REG(0x7F005424)
#define UBRDIV1_REG __REG(0x7F005428)
#define UDIVSLOT1_REG __REG(0x7F00542c)
#define UINTP1_REG __REG(0x7F005430)
#define UINTSP1_REG __REG(0x7F005434)
#define UINTM1_REG __REG(0x7F005438)
#define UTRSTAT_TX_EMPTY BIT2
#define UTRSTAT_RX_READY BIT0
#define UART_ERR_MASK 0xF
/*
* PWM timer
*/
#define ELFIN_TIMER_BASE 0x7F006000
#define TCFG0_REG __REG(0x7F006000)
#define TCFG1_REG __REG(0x7F006004)
#define TCON_REG __REG(0x7F006008)
#define TCNTB0_REG __REG(0x7F00600c)
#define TCMPB0_REG __REG(0x7F006010)
#define TCNTO0_REG __REG(0x7F006014)
#define TCNTB1_REG __REG(0x7F006018)
#define TCMPB1_REG __REG(0x7F00601c)
#define TCNTO1_REG __REG(0x7F006020)
#define TCNTB2_REG __REG(0x7F006024)
#define TCMPB2_REG __REG(0x7F006028)
#define TCNTO2_REG __REG(0x7F00602c)
#define TCNTB3_REG __REG(0x7F006030)
#define TCMPB3_REG __REG(0x7F006034)
#define TCNTO3_REG __REG(0x7F006038)
#define TCNTB4_REG __REG(0x7F00603c)
#define TCNTO4_REG __REG(0x7F006040)
/* Fields */
#define fTCFG0_DZONE Fld(8,16) /* the dead zone length (= timer 0) */
#define fTCFG0_PRE1 Fld(8,8) /* prescaler value for time 2,3,4 */
#define fTCFG0_PRE0 Fld(8,0) /* prescaler value for time 0,1 */
#define fTCFG1_MUX4 Fld(4,16)
/* bits */
#define TCFG0_DZONE(x) FInsrt((x), fTCFG0_DZONE)
#define TCFG0_PRE1(x) FInsrt((x), fTCFG0_PRE1)
#define TCFG0_PRE0(x) FInsrt((x), fTCFG0_PRE0)
#define TCON_4_AUTO (1 << 22) /* auto reload on/off for Timer 4 */
#define TCON_4_UPDATE (1 << 21) /* manual Update TCNTB4 */
#define TCON_4_ONOFF (1 << 20) /* 0: Stop, 1: start Timer 4 */
#define COUNT_4_ON (TCON_4_ONOFF*1)
#define COUNT_4_OFF (TCON_4_ONOFF*0)
#define TCON_3_AUTO (1 << 19) /* auto reload on/off for Timer 3 */
#define TIMER3_ATLOAD_ON (TCON_3_AUTO*1)
#define TIMER3_ATLAOD_OFF FClrBit(TCON, TCON_3_AUTO)
#define TCON_3_INVERT (1 << 18) /* 1: Inverter on for TOUT3 */
#define TIMER3_IVT_ON (TCON_3_INVERT*1)
#define TIMER3_IVT_OFF (FClrBit(TCON, TCON_3_INVERT))
#define TCON_3_MAN (1 << 17) /* manual Update TCNTB3,TCMPB3 */
#define TIMER3_MANUP (TCON_3_MAN*1)
#define TIMER3_NOP (FClrBit(TCON, TCON_3_MAN))
#define TCON_3_ONOFF (1 << 16) /* 0: Stop, 1: start Timer 3 */
#define TIMER3_ON (TCON_3_ONOFF*1)
#define TIMER3_OFF (FClrBit(TCON, TCON_3_ONOFF))
/* macros */
#define GET_PRESCALE_TIMER4(x) FExtr((x), fTCFG0_PRE1)
#define GET_DIVIDER_TIMER4(x) FExtr((x), fTCFG1_MUX4)
/*
* RTC Controller
*/
#define ELFIN_RTC_BASE 0x7e005000
#define RTCCON_REG __REG(0x7e005040)
#define TICNT_REG __REG(0x7e005044)
#define RTCALM_REG __REG(0x7e005050)
#define ALMSEC_REG __REG(0x7e005054)
#define ALMMIN_REG __REG(0x7e005058)
#define ALMHOUR_REG __REG(0x7e00505c)
#define ALMDATE_REG __REG(0x7e005060)
#define ALMMON_REG __REG(0x7e005064)
#define ALMYEAR_REG __REG(0x7e005068)
#define BCDSEC_REG __REG(0x7e005070)
#define BCDMIN_REG __REG(0x7e005074)
#define BCDHOUR_REG __REG(0x7e005078)
#define BCDDATE_REG __REG(0x7e00507c)
#define BCDDAY_REG __REG(0x7e005080)
#define BCDMON_REG __REG(0x7e005084)
#define BCDYEAR_REG __REG(0x7e005088)
/*
* USB2.0 HS OTG (Chapter 26)
*/
#define USBOTG_LINK_BASE (0x7C000000)
#define USBOTG_PHY_BASE (0x7C100000)
/* Core Global Registers */
#define S3C_OTG_GOTGCTL (USBOTG_LINK_BASE + 0x000) /* OTG Control & Status */
#define S3C_OTG_GOTGINT (USBOTG_LINK_BASE + 0x004) /* OTG Interrupt */
#define S3C_OTG_GAHBCFG (USBOTG_LINK_BASE + 0x008) /* Core AHB Configuration */
#define S3C_OTG_GUSBCFG (USBOTG_LINK_BASE + 0x00C) /* Core USB Configuration */
#define S3C_OTG_GRSTCTL (USBOTG_LINK_BASE + 0x010) /* Core Reset */
#define S3C_OTG_GINTSTS (USBOTG_LINK_BASE + 0x014) /* Core Interrupt */
#define S3C_OTG_GINTMSK (USBOTG_LINK_BASE + 0x018) /* Core Interrupt Mask */
#define S3C_OTG_GRXSTSR (USBOTG_LINK_BASE + 0x01C) /* Receive Status Debug Read/Status Read */
#define S3C_OTG_GRXSTSP (USBOTG_LINK_BASE + 0x020) /* Receive Status Debug Pop/Status Pop */
#define S3C_OTG_GRXFSIZ (USBOTG_LINK_BASE + 0x024) /* Receive FIFO Size */
#define S3C_OTG_GNPTXFSIZ (USBOTG_LINK_BASE + 0x028) /* Non-Periodic Transmit FIFO Size */
#define S3C_OTG_GNPTXSTS (USBOTG_LINK_BASE + 0x02C) /* Non-Periodic Transmit FIFO/Queue Status */
#define S3C_OTG_HPTXFSIZ (USBOTG_LINK_BASE + 0x100) /* Host Periodic Transmit FIFO Size */
#define S3C_OTG_DPTXFSIZ1 (USBOTG_LINK_BASE + 0x104) /* Device Periodic Transmit FIFO-1 Size */
#define S3C_OTG_DPTXFSIZ2 (USBOTG_LINK_BASE + 0x108) /* Device Periodic Transmit FIFO-2 Size */
#define S3C_OTG_DPTXFSIZ3 (USBOTG_LINK_BASE + 0x10C) /* Device Periodic Transmit FIFO-3 Size */
#define S3C_OTG_DPTXFSIZ4 (USBOTG_LINK_BASE + 0x110) /* Device Periodic Transmit FIFO-4 Size */
#define S3C_OTG_DPTXFSIZ5 (USBOTG_LINK_BASE + 0x114) /* Device Periodic Transmit FIFO-5 Size */
#define S3C_OTG_DPTXFSIZ6 (USBOTG_LINK_BASE + 0x118) /* Device Periodic Transmit FIFO-6 Size */
#define S3C_OTG_DPTXFSIZ7 (USBOTG_LINK_BASE + 0x11C) /* Device Periodic Transmit FIFO-7 Size */
#define S3C_OTG_DPTXFSIZ8 (USBOTG_LINK_BASE + 0x120) /* Device Periodic Transmit FIFO-8 Size */
#define S3C_OTG_DPTXFSIZ9 (USBOTG_LINK_BASE + 0x124) /* Device Periodic Transmit FIFO-9 Size */
#define S3C_OTG_DPTXFSIZ10 (USBOTG_LINK_BASE + 0x128) /* Device Periodic Transmit FIFO-10 Size */
#define S3C_OTG_DPTXFSIZ11 (USBOTG_LINK_BASE + 0x12C) /* Device Periodic Transmit FIFO-11 Size */
#define S3C_OTG_DPTXFSIZ12 (USBOTG_LINK_BASE + 0x130) /* Device Periodic Transmit FIFO-12 Size */
#define S3C_OTG_DPTXFSIZ13 (USBOTG_LINK_BASE + 0x134) /* Device Periodic Transmit FIFO-13 Size */
#define S3C_OTG_DPTXFSIZ14 (USBOTG_LINK_BASE + 0x138) /* Device Periodic Transmit FIFO-14 Size */
#define S3C_OTG_DPTXFSIZ15 (USBOTG_LINK_BASE + 0x13C) /* Device Periodic Transmit FIFO-15 Size */
/* Host Global Registers */
#define S3C_OTG_HCFG (USBOTG_LINK_BASE + 0x400) /* Host Configuration */
#define S3C_OTG_HFIR (USBOTG_LINK_BASE + 0x404) /* Host Frame Interval */
#define S3C_OTG_HFNUM (USBOTG_LINK_BASE + 0x408) /* Host Frame Number/Frame Time Remaining */
#define S3C_OTG_HPTXSTS (USBOTG_LINK_BASE + 0x410) /* Host Periodic Transmit FIFO/Queue Status */
#define S3C_OTG_HAINT (USBOTG_LINK_BASE + 0x414) /* Host All Channels Interrupt */
#define S3C_OTG_HAINTMSK (USBOTG_LINK_BASE + 0x418) /* Host All Channels Interrupt Mask */
/* Host Port Control & Status Registers */
#define S3C_OTG_HPRT (USBOTG_LINK_BASE + 0x440) /* Host Port Control & Status */
/* Host Channel-Specific Registers */
#define S3C_OTG_HCCHAR0 (USBOTG_LINK_BASE + 0x500) /* Host Channel-0 Characteristics */
#define S3C_OTG_HCSPLT0 (USBOTG_LINK_BASE + 0x504) /* Host Channel-0 Split Control */
#define S3C_OTG_HCINT0 (USBOTG_LINK_BASE + 0x508) /* Host Channel-0 Interrupt */
#define S3C_OTG_HCINTMSK0 (USBOTG_LINK_BASE + 0x50C) /* Host Channel-0 Interrupt Mask */
#define S3C_OTG_HCTSIZ0 (USBOTG_LINK_BASE + 0x510) /* Host Channel-0 Transfer Size */
#define S3C_OTG_HCDMA0 (USBOTG_LINK_BASE + 0x514) /* Host Channel-0 DMA Address */
/* Device Global Registers */
#define S3C_OTG_DCFG (USBOTG_LINK_BASE + 0x800) /* Device Configuration */
#define S3C_OTG_DCTL (USBOTG_LINK_BASE + 0x804) /* Device Control */
#define S3C_OTG_DSTS (USBOTG_LINK_BASE + 0x808) /* Device Status */
#define S3C_OTG_DIEPMSK (USBOTG_LINK_BASE + 0x810) /* Device IN Endpoint Common Interrupt Mask */
#define S3C_OTG_DOEPMSK (USBOTG_LINK_BASE + 0x814) /* Device OUT Endpoint Common Interrupt Mask */
#define S3C_OTG_DAINT (USBOTG_LINK_BASE + 0x818) /* Device All Endpoints Interrupt */
#define S3C_OTG_DAINTMSK (USBOTG_LINK_BASE + 0x81C) /* Device All Endpoints Interrupt Mask */
#define S3C_OTG_DTKNQR1 (USBOTG_LINK_BASE + 0x820) /* Device IN Token Sequence Learning Queue Read 1 */
#define S3C_OTG_DTKNQR2 (USBOTG_LINK_BASE + 0x824) /* Device IN Token Sequence Learning Queue Read 2 */
#define S3C_OTG_DVBUSDIS (USBOTG_LINK_BASE + 0x828) /* Device VBUS Discharge Time */
#define S3C_OTG_DVBUSPULSE (USBOTG_LINK_BASE + 0x82C) /* Device VBUS Pulsing Time */
#define S3C_OTG_DTKNQR3 (USBOTG_LINK_BASE + 0x830) /* Device IN Token Sequence Learning Queue Read 3 */
#define S3C_OTG_DTKNQR4 (USBOTG_LINK_BASE + 0x834) /* Device IN Token Sequence Learning Queue Read 4 */
/* Device Logical IN Endpoint-Specific Registers */
#define S3C_OTG_DIEPCTL0 (USBOTG_LINK_BASE + 0x900) /* Device IN Endpoint 0 Control */
#define S3C_OTG_DIEPINT0 (USBOTG_LINK_BASE + 0x908) /* Device IN Endpoint 0 Interrupt */
#define S3C_OTG_DIEPTSIZ0 (USBOTG_LINK_BASE + 0x910) /* Device IN Endpoint 0 Transfer Size */
#define S3C_OTG_DIEPDMA0 (USBOTG_LINK_BASE + 0x914) /* Device IN Endpoint 0 DMA Address */
/* Device Logical OUT Endpoint-Specific Registers */
#define S3C_OTG_DOEPCTL0 (USBOTG_LINK_BASE + 0xB00) /* Device OUT Endpoint 0 Control */
#define S3C_OTG_DOEPINT0 (USBOTG_LINK_BASE + 0xB08) /* Device OUT Endpoint 0 Interrupt */
#define S3C_OTG_DOEPTSIZ0 (USBOTG_LINK_BASE + 0xB10) /* Device OUT Endpoint 0 Transfer Size */
#define S3C_OTG_DOEPDMA0 (USBOTG_LINK_BASE + 0xB14) /* Device OUT Endpoint 0 DMA Address */
/* Power & clock gating registers */
#define S3C_OTG_PCGCCTRL (USBOTG_LINK_BASE + 0xE00)
/* Endpoint FIFO address */
#define S3C_OTG_EP0_FIFO (USBOTG_LINK_BASE + 0x1000)
/* OTG PHY CORE REGISTERS */
#define S3C_OTG_PHYPWR (USBOTG_PHY_BASE+0x00)
#define S3C_OTG_PHYCTRL (USBOTG_PHY_BASE+0x04)
#define S3C_OTG_RSTCON (USBOTG_PHY_BASE+0x08)
/* include common stuff */
#ifndef __ASSEMBLY__
#if 0
static inline S3C2410_SDI * S3C2410_GetBase_SDI(void)
{
return (S3C2410_SDI *)ELFIN_SDI_BASE;
}
#endif
#else /* #ifndef __ASSEMBLY__ */
/* watchdog */
#define WTCON_OFFSET 0x00
/* LCD controller */
#define LCDBGCON_OFFSET 0x5c
#endif /* #ifndef __ASSEMBLY__ */
/* PENDING BIT */
#define BIT_EINT0 (0x1)
#define BIT_EINT1 (0x1<<1)
#define BIT_EINT2 (0x1<<2)
#define BIT_EINT3 (0x1<<3)
#define BIT_EINT4_7 (0x1<<4)
#define BIT_EINT8_23 (0x1<<5)
#define BIT_BAT_FLT (0x1<<7)
#define BIT_TICK (0x1<<8)
#define BIT_WDT (0x1<<9)
#define BIT_TIMER0 (0x1<<10)
#define BIT_TIMER1 (0x1<<11)
#define BIT_TIMER2 (0x1<<12)
#define BIT_TIMER3 (0x1<<13)
#define BIT_TIMER4 (0x1<<14)
#define BIT_UART2 (0x1<<15)
#define BIT_LCD (0x1<<16)
#define BIT_DMA0 (0x1<<17)
#define BIT_DMA1 (0x1<<18)
#define BIT_DMA2 (0x1<<19)
#define BIT_DMA3 (0x1<<20)
#define BIT_SDI (0x1<<21)
#define BIT_SPI0 (0x1<<22)
#define BIT_UART1 (0x1<<23)
#define BIT_USBH (0x1<<26)
#define BIT_IIC (0x1<<27)
#define BIT_UART0 (0x1<<28)
#define BIT_SPI1 (0x1<<29)
#define BIT_RTC (0x1<<30)
#define BIT_ADC (0x1<<31)
#define BIT_ALLMSK (0xFFFFFFFF)
#endif /*__S3C6410_H__*/
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