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53 lines
1.5 KiB
C
53 lines
1.5 KiB
C
/*
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* jz4730_board.h
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*
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* JZ4730 board definitions.
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*
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* Copyright (c) 2005-2008 Ingenic Semiconductor Inc.
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*
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*/
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#ifndef __JZ4730_BOARD_H__
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#define __JZ4730_BOARD_H__
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/*-------------------------------------------------------------------
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* Frequency of the external OSC in Hz.
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*/
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#define CFG_EXTAL 12000000
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/*-------------------------------------------------------------------
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* CPU speed.
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*/
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#define CFG_CPU_SPEED 336000000
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/*-------------------------------------------------------------------
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* Serial console.
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*/
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#define CFG_UART_BASE UART3_BASE
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#define CONFIG_BAUDRATE 9600
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/*-------------------------------------------------------------------
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* SDRAM info.
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*/
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// SDRAM paramters
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#define CFG_SDRAM_BW16 0 /* Data bus width: 0-32bit, 1-16bit */
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#define CFG_SDRAM_BANK4 1 /* Banks each chip: 0-2bank, 1-4bank */
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#define CFG_SDRAM_ROW 13 /* Row address: 11 to 13 */
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#define CFG_SDRAM_COL 9 /* Column address: 8 to 12 */
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#define CFG_SDRAM_CASL 2 /* CAS latency: 2 or 3 */
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// SDRAM Timings, unit: ns
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#define CFG_SDRAM_TRAS 45 /* RAS# Active Time */
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#define CFG_SDRAM_RCD 20 /* RAS# to CAS# Delay */
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#define CFG_SDRAM_TPC 20 /* RAS# Precharge Time */
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#define CFG_SDRAM_TRWL 7 /* Write Latency Time */
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#define CFG_SDRAM_TREF 7812 /* Refresh period: 8192 refresh cycles/64ms */
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/*-------------------------------------------------------------------
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* Linux kernel command line.
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*/
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#define CFG_CMDLINE "mem=32M console=ttyS0,57600n8 ip=off rootfstype=yaffs2 root=/dev/mtdblock2 rw init=/etc/inittab"
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#endif /* __JZ4730_BOARD_H__ */
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