xue/kicad/xue-rnc/xue-rnc.sch

EESchema Schematic File Version 2  date Fri 13 Aug 2010 11:23:32 AM COT
LIBS:power,../library/v0402mhs03,../library/usb-48204-0001,../library/microsmd075f,../library/mic2550ayts,../library/rj45-48025,../library/xue-nv,../library/xc6slx75fgg484,../library/xc6slx45fgg484,../library/micron_mobile_ddr,../library/micron_ddr_512Mb,../library/k8001,device,transistors,conn,linear,regul,74xx,cmos4000,adc-dac,memory,xilinx,special,microcontrollers,dsp,microchip,analog_switches,motorola,texas,intel,audio,interface,digital-audio,philips,display,cypress,siliconi,opto,atmel,contrib,valves,../library/pasives-connectors,./xue-rnc.cache
EELAYER 24  0
EELAYER END
$Descr A3 16535 11700
Sheet 1 6
Title ""
Date "13 aug 2010"
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Kmarq B 10650 3450 "Warning SheetLabel FWE_N not connected to HLabel" F=1
Wire Wire Line
	10650 3950 9300 3950
Wire Wire Line
	10650 3750 9300 3750
Wire Wire Line
	10650 3650 9300 3650
Wire Wire Line
	10650 3450 9300 3450
Wire Bus Line
	10650 4050 9300 4050
Wire Wire Line
	10600 6700 9300 6700
Wire Wire Line
	9300 3000 10650 3000
Wire Bus Line
	10600 7200 9300 7200
Wire Bus Line
	9300 7600 10600 7600
Wire Wire Line
	10650 5300 9300 5300
Wire Wire Line
	10650 5100 9300 5100
Wire Wire Line
	9300 7900 10600 7900
Wire Wire Line
	9300 7700 10600 7700
Wire Wire Line
	9300 7500 10600 7500
Wire Wire Line
	9300 7300 10600 7300
Wire Wire Line
	9300 7000 10600 7000
Wire Wire Line
	9300 6600 10600 6600
Wire Wire Line
	9300 6350 10600 6350
Wire Bus Line
	4700 2950 5950 2950
Wire Wire Line
	4700 3350 5950 3350
Wire Wire Line
	4700 3450 5950 3450
Wire Wire Line
	4700 3650 5950 3650
Wire Wire Line
	4700 4500 5950 4500
Wire Wire Line
	4700 4350 5950 4350
Wire Wire Line
	4700 4900 5950 4900
Wire Wire Line
	4700 6400 5950 6400
Wire Wire Line
	4700 5500 5950 5500
Wire Wire Line
	4700 5800 5950 5800
Wire Bus Line
	4700 5150 5950 5150
Wire Wire Line
	4700 4000 5950 4000
Wire Wire Line
	4700 6050 5950 6050
Wire Bus Line
	4700 5050 5950 5050
Wire Bus Line
	5950 5050 5950 5100
Wire Wire Line
	4700 6150 5950 6150
Wire Wire Line
	5950 4100 4700 4100
Wire Bus Line
	4700 3050 5950 3050
Wire Wire Line
	4700 5400 5950 5400
Wire Wire Line
	4700 5700 5950 5700
Wire Wire Line
	4700 6300 5950 6300
Wire Bus Line
	4700 5250 5950 5250
Wire Wire Line
	4700 6550 5950 6550
Wire Wire Line
	4700 5950 5950 5950
Wire Wire Line
	4700 4250 5950 4250
Wire Wire Line
	4700 3900 5950 3900
Wire Wire Line
	4700 3750 5950 3750
Wire Wire Line
	4700 2800 5950 2800
Wire Bus Line
	4700 3150 5950 3150
Wire Wire Line
	9300 6500 10600 6500
Wire Wire Line
	10600 6900 9300 6900
Wire Wire Line
	9300 7400 10600 7400
Wire Wire Line
	9300 7800 10600 7800
Wire Wire Line
	10650 5000 9300 5000
Wire Wire Line
	10650 5200 9300 5200
Wire Wire Line
	10650 5400 9300 5400
Wire Wire Line
	9300 2900 10650 2900
Wire Bus Line
	9300 3100 10650 3100
Wire Wire Line
	10600 6800 9300 6800
Wire Wire Line
	10650 3350 9300 3350
Wire Wire Line
	9300 3550 10650 3550
Wire Wire Line
	10650 3850 9300 3850
$Sheet
S 10650 4800 1150 750 
U 4C5F1EDC
F0 "USB" 60
F1 "USB.sch" 60
F2 "USBA_SPD" B L 10650 5000 60 
F3 "USBA_OE_N" B L 10650 5100 60 
F4 "USBA_RCV" B L 10650 5200 60 
F5 "USBA_VP" B L 10650 5300 60 
F6 "USBA_VM" B L 10650 5400 60 
$EndSheet
Text Notes 12850 10750 0    60   ~ 0
Copyright: Andres.Calderon@emQbit.com  /  Juan.Brinez@emQbit.com
$Sheet
S 5950 2700 3350 5800
U 4C431A63
F0 "FPGA Spartan6" 60
F1 "FPGA.sch" 60
F2 "M1_CLK" O L 5950 4000 60 
F3 "M1_CLK#" O L 5950 4100 60 
F4 "M0_CLK" O L 5950 6050 60 
F5 "M0_CLK#" O L 5950 6150 60 
F6 "M0_A[0..12]" O L 5950 5150 60 
F7 "M1_A[0..12]" O L 5950 3050 60 
F8 "M0_DQ[0..15]" B L 5950 5050 60 
F9 "M0_UDQS" O L 5950 5400 60 
F10 "M0_LDM" O L 5950 5800 60 
F11 "M0_LDQS" O L 5950 5500 60 
F12 "M0_UDM" O L 5950 5700 60 
F13 "M0_RAS#" O L 5950 6400 60 
F14 "M0_WE#" O L 5950 6550 60 
F15 "M0_CKE" O L 5950 5950 60 
F16 "M0_CAS#" O L 5950 6300 60 
F17 "M1_CAS#" O L 5950 4250 60 
F18 "M1_CKE" O L 5950 3900 60 
F19 "M0_CS#" O L 5950 4900 60 
F20 "M1_CS#" O L 5950 2800 60 
F21 "M1_WE#" O L 5950 4500 60 
F22 "M1_RAS#" O L 5950 4350 60 
F23 "M1_UDM" O L 5950 3650 60 
F24 "M1_LDQS" O L 5950 3450 60 
F25 "M1_LDM" O L 5950 3750 60 
F26 "M1_UDQS" O L 5950 3350 60 
F27 "M1_DQ[0..15]" B L 5950 2950 60 
F28 "M1_BA[0..1]" O L 5950 3150 60 
F29 "M0_BA[0..1]" O L 5950 5250 60 
F30 "USBA_VM" B R 9300 5400 60 
F31 "USBA_VP" B R 9300 5300 60 
F32 "USBA_RCV" B R 9300 5200 60 
F33 "USBA_OE_N" B R 9300 5100 60 
F34 "USBA_SPD" B R 9300 5000 60 
F35 "ETH_CLK" B R 9300 7900 60 
F36 "ETH_RXC" B R 9300 6500 60 
F37 "ETH_TXC" B R 9300 7500 60 
F38 "ETH_TXD[0..3]" O R 9300 7600 60 
F39 "ETH_TXEN" B R 9300 7700 60 
F40 "ETH_TXER" B R 9300 7800 60 
F41 "ETH_RXER" B R 9300 7400 60 
F42 "ETH_RXDV" B R 9300 7300 60 
F43 "ETH_RXD[0..3]" I R 9300 7200 60 
F44 "ETH_RESET_N" B R 9300 6600 60 
F45 "ETH_MDIO" B R 9300 6900 60 
F46 "ETH_MDC" B R 9300 7000 60 
F47 "ETH_INT" B R 9300 6350 60 
F48 "SD_CLK" B R 9300 2900 60 
F49 "SD_CMD" B R 9300 3000 60 
F50 "SD_DAT[0..3]" B R 9300 3100 60 
F51 "ETH_CRS" I R 9300 6700 60 
F52 "ETH_COL" I R 9300 6800 60 
F53 "NF_D[0..7]" B R 9300 4050 60 
$EndSheet
$Sheet
S 10600 6250 1300 1800
U 4C4320F3
F0 "Ethernet Phy" 60
F1 "eth_phy.sch" 60
F2 "ETH_RXC" O L 10600 6500 60 
F3 "ETH_RST_N" I L 10600 6600 60 
F4 "ETH_CRS" O L 10600 6700 60 
F5 "ETH_COL" O L 10600 6800 60 
F6 "ETH_MDIO" B L 10600 6900 60 
F7 "ETH_MDC" I L 10600 7000 60 
F8 "ETH_RXD[0..3]" O L 10600 7200 60 
F9 "ETH_RXDV" O L 10600 7300 60 
F10 "ETH_RXER" O L 10600 7400 60 
F11 "ETH_TXC" B L 10600 7500 60 
F12 "ETH_TXD[0..3]" I L 10600 7600 60 
F13 "ETH_TXEN" I L 10600 7700 60 
F14 "ETH_TXER" I L 10600 7800 60 
F15 "ETH_CLK" I L 10600 7900 60 
F16 "ETH_INT" O L 10600 6350 60 
$EndSheet
$Sheet
S 10650 2700 1150 1850
U 4C4227FE
F0 "Non volatile memories" 60
F1 "NV_MEMORIES.sch" 60
F2 "SD_CMD" I L 10650 3000 60 
F3 "SD_CLK" I L 10650 2900 60 
F4 "SD_DAT[0..3]" B L 10650 3100 60 
F5 "NF_D[0..7]" B L 10650 4050 60 
F6 "FWE_N" B L 10650 3450 60 
F7 "NF_ALE" B L 10650 3550 60 
F8 "NF_CLE" B L 10650 3650 60 
F9 "NF_WE_N" B L 10650 3750 60 
F10 "NF_CS1_N" B L 10650 3350 60 
F11 "NF_RE_N" B L 10650 3850 60 
F12 "NF_RNB" B L 10650 3950 60 
$EndSheet
$Sheet
S 3600 2700 1100 4000
U 4C421DD3
F0 "DDR Banks" 60
F1 "DRAM.sch" 60
F2 "M0_BA[0..1]" I R 4700 5250 60 
F3 "M1_BA[0..1]" I R 4700 3150 60 
F4 "M0_WE#" I R 4700 6550 60 
F5 "M0_RAS#" I R 4700 6400 60 
F6 "M1_RAS#" I R 4700 4350 60 
F7 "M1_WE#" I R 4700 4500 60 
F8 "M0_CAS#" I R 4700 6300 60 
F9 "M0_CKE" I R 4700 5950 60 
F10 "M0_CLK" I R 4700 6050 60 
F11 "M0_CLK#" I R 4700 6150 60 
F12 "M0_CS#" I R 4700 4900 60 
F13 "M1_CLK#" I R 4700 4100 60 
F14 "M1_CLK" I R 4700 4000 60 
F15 "M1_CKE" I R 4700 3900 60 
F16 "M1_CAS#" I R 4700 4250 60 
F17 "M0_DQ[0..15]" B R 4700 5050 60 
F18 "M0_UDM" I R 4700 5700 60 
F19 "M0_LDQS" I R 4700 5500 60 
F20 "M0_A[0..12]" I R 4700 5150 60 
F21 "M0_LDM" I R 4700 5800 60 
F22 "M0_UDQS" I R 4700 5400 60 
F23 "M1_UDQS" I R 4700 3350 60 
F24 "M1_LDM" I R 4700 3750 60 
F25 "M1_LDQS" I R 4700 3450 60 
F26 "M1_UDM" I R 4700 3650 60 
F27 "M1_CS#" I R 4700 2800 60 
F28 "M1_A[0..12]" I R 4700 3050 60 
F29 "M1_DQ[0..15]" B R 4700 2950 60 
$EndSheet
$EndSCHEMATC
FPGA decoupling capacitors 2010-08-13 19:24:39 +03:00			`EESchema Schematic File Version 2 date Fri 13 Aug 2010 11:23:32 AM COT`
			LIBS:power,../library/v0402mhs03,../library/usb-48204-0001,../library/microsmd075f,../library/mic2550ayts,../library/rj45-48025,../library/xue-nv,../library/xc6slx75fgg484,../library/xc6slx45fgg484,../library/micron_mobile_ddr,../library/micron_ddr_512Mb,../library/k8001,device,transistors,conn,linear,regul,74xx,cmos4000,adc-dac,memory,xilinx,special,microcontrollers,dsp,microchip,analog_switches,motorola,texas,intel,audio,interface,digital-audio,philips,display,cypress,siliconi,opto,atmel,contrib,valves,../library/pasives-connectors,./xue-rnc.cache
initial import 2010-07-24 14:58:53 +03:00			`EELAYER 24 0`
			`EELAYER END`
USB and MICROSD footprints added 2010-08-09 01:54:09 +03:00			`$Descr A3 16535 11700`
			`Sheet 1 6`
initial import 2010-07-24 14:58:53 +03:00			`Title ""`
fix 2010-08-13 05:12:14 +03:00			`Date "13 aug 2010"`
initial import 2010-07-24 14:58:53 +03:00			`Rev ""`
			`Comp ""`
			`Comment1 ""`
			`Comment2 ""`
			`Comment3 ""`
			`Comment4 ""`
			`$EndDescr`
FPGA decoupling capacitors 2010-08-13 19:24:39 +03:00			`Kmarq B 10650 3450 "Warning SheetLabel FWE_N not connected to HLabel" F=1`
Fixing USB connections 2010-08-11 05:25:32 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`10650 3950 9300 3950`
			`Wire Wire Line`
			`10650 3750 9300 3750`
			`Wire Wire Line`
			`10650 3650 9300 3650`
			`Wire Wire Line`
			`10650 3450 9300 3450`
DDR de-coupling caps. added 2010-08-11 01:38:37 +03:00			`Wire Bus Line`
fix 2010-08-13 01:18:08 +03:00			`10650 4050 9300 4050`
Ethernet-phy and USB connected to FPGA 2010-08-09 23:37:18 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`10600 6700 9300 6700`
Ethernet-phy and USB connected to FPGA 2010-08-09 23:37:18 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`9300 3000 10650 3000`
			`Wire Bus Line`
			`10600 7200 9300 7200`
			`Wire Bus Line`
			`9300 7600 10600 7600`
Ethernet-phy and USB connected to FPGA 2010-08-09 23:37:18 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`10650 5300 9300 5300`
Ethernet-phy and USB connected to FPGA 2010-08-09 23:37:18 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`10650 5100 9300 5100`
Ethernet-phy and USB connected to FPGA 2010-08-09 23:37:18 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`9300 7900 10600 7900`
Ethernet-phy and USB connected to FPGA 2010-08-09 23:37:18 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`9300 7700 10600 7700`
Ethernet-phy and USB connected to FPGA 2010-08-09 23:37:18 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`9300 7500 10600 7500`
Ethernet-phy and USB connected to FPGA 2010-08-09 23:37:18 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`9300 7300 10600 7300`
			`Wire Wire Line`
			`9300 7000 10600 7000`
			`Wire Wire Line`
			`9300 6600 10600 6600`
			`Wire Wire Line`
			`9300 6350 10600 6350`
ddr address and data has been conected to the FPGA 2010-08-05 04:50:31 +03:00			`Wire Bus Line`
fix 2010-08-13 01:18:08 +03:00			`4700 2950 5950 2950`
some ethernet phy conections 2010-07-28 04:09:20 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`4700 3350 5950 3350`
only one wire connected 2010-07-28 14:48:02 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`4700 3450 5950 3450`
more fpga ddr lines has been connected 2010-08-09 06:53:21 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`4700 3650 5950 3650`
more fpga ddr lines has been connected 2010-08-09 06:53:21 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`4700 4500 5950 4500`
more fpga ddr lines has been connected 2010-08-09 06:53:21 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`4700 4350 5950 4350`
more fpga ddr lines has been connected 2010-08-09 06:53:21 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`4700 4900 5950 4900`
more fpga ddr lines has been connected 2010-08-09 06:53:21 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`4700 6400 5950 6400`
more fpga ddr lines has been connected 2010-08-09 06:53:21 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`4700 5500 5950 5500`
more fpga ddr lines has been connected 2010-08-09 06:53:21 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`4700 5800 5950 5800`
initial import 2010-07-24 14:58:53 +03:00			`Wire Bus Line`
fix 2010-08-13 01:18:08 +03:00			`4700 5150 5950 5150`
some ethernet phy conections 2010-07-28 04:09:20 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`4700 4000 5950 4000`
some ethernet phy conections 2010-07-28 04:09:20 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`4700 6050 5950 6050`
ddr mobile replaced by ddr 2010-08-04 05:23:17 +03:00			`Wire Bus Line`
fix 2010-08-13 01:18:08 +03:00			`4700 5050 5950 5050`
more fpga ddr lines has been connected 2010-08-09 06:53:21 +03:00			`Wire Bus Line`
fix 2010-08-13 01:18:08 +03:00			`5950 5050 5950 5100`
more fpga ddr lines has been connected 2010-08-09 06:53:21 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`4700 6150 5950 6150`
more fpga ddr lines has been connected 2010-08-09 06:53:21 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`5950 4100 4700 4100`
more fpga ddr lines has been connected 2010-08-09 06:53:21 +03:00			`Wire Bus Line`
fix 2010-08-13 01:18:08 +03:00			`4700 3050 5950 3050`
more fpga ddr lines has been connected 2010-08-09 06:53:21 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`4700 5400 5950 5400`
more fpga ddr lines has been connected 2010-08-09 06:53:21 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`4700 5700 5950 5700`
more fpga ddr lines has been connected 2010-08-09 06:53:21 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`4700 6300 5950 6300`
			`Wire Bus Line`
			`4700 5250 5950 5250`
more fpga ddr lines has been connected 2010-08-09 06:53:21 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`4700 6550 5950 6550`
more fpga ddr lines has been connected 2010-08-09 06:53:21 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`4700 5950 5950 5950`
more fpga ddr lines has been connected 2010-08-09 06:53:21 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`4700 4250 5950 4250`
more fpga ddr lines has been connected 2010-08-09 06:53:21 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`4700 3900 5950 3900`
more fpga ddr lines has been connected 2010-08-09 06:53:21 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`4700 3750 5950 3750`
more fpga ddr lines has been connected 2010-08-09 06:53:21 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`4700 2800 5950 2800`
more fpga ddr lines has been connected 2010-08-09 06:53:21 +03:00			`Wire Bus Line`
fix 2010-08-13 01:18:08 +03:00			`4700 3150 5950 3150`
Ethernet-phy and USB connected to FPGA 2010-08-09 23:37:18 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`9300 6500 10600 6500`
Ethernet-phy and USB connected to FPGA 2010-08-09 23:37:18 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`10600 6900 9300 6900`
Ethernet-phy and USB connected to FPGA 2010-08-09 23:37:18 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`9300 7400 10600 7400`
Ethernet-phy and USB connected to FPGA 2010-08-09 23:37:18 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`9300 7800 10600 7800`
Ethernet-phy and USB connected to FPGA 2010-08-09 23:37:18 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`10650 5000 9300 5000`
Ethernet-phy and USB connected to FPGA 2010-08-09 23:37:18 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`10650 5200 9300 5200`
SD connector attached to th S6 2010-08-11 02:09:38 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`10650 5400 9300 5400`
SD connector attached to th S6 2010-08-11 02:09:38 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`9300 2900 10650 2900`
SD connector attached to th S6 2010-08-11 02:09:38 +03:00			`Wire Bus Line`
fix 2010-08-13 01:18:08 +03:00			`9300 3100 10650 3100`
SD connector attached to th S6 2010-08-11 02:09:38 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`10600 6800 9300 6800`
Fixing USB connections 2010-08-11 05:25:32 +03:00			`Wire Wire Line`
fix 2010-08-13 01:18:08 +03:00			`10650 3350 9300 3350`
			`Wire Wire Line`
			`9300 3550 10650 3550`
			`Wire Wire Line`
			`10650 3850 9300 3850`
Fixing USB connections 2010-08-11 05:25:32 +03:00			`$Sheet`
			`S 10650 4800 1150 750`
			`U 4C5F1EDC`
			`F0 "USB" 60`
			`F1 "USB.sch" 60`
			`F2 "USBA_SPD" B L 10650 5000 60`
			`F3 "USBA_OE_N" B L 10650 5100 60`
			`F4 "USBA_RCV" B L 10650 5200 60`
			`F5 "USBA_VP" B L 10650 5300 60`
			`F6 "USBA_VM" B L 10650 5400 60`
			`$EndSheet`
			`Text Notes 12850 10750 0 60 ~ 0`
			`Copyright: Andres.Calderon@emQbit.com / Juan.Brinez@emQbit.com`
initial import 2010-07-24 14:58:53 +03:00			`$Sheet`
USB and MICROSD footprints added 2010-08-09 01:54:09 +03:00			`S 5950 2700 3350 5800`
initial import 2010-07-24 14:58:53 +03:00			`U 4C431A63`
			`F0 "FPGA Spartan6" 60`
			`F1 "FPGA.sch" 60`
USB and MICROSD footprints added 2010-08-09 01:54:09 +03:00			`F2 "M1_CLK" O L 5950 4000 60`
			`F3 "M1_CLK#" O L 5950 4100 60`
			`F4 "M0_CLK" O L 5950 6050 60`
			`F5 "M0_CLK#" O L 5950 6150 60`
DDR de-coupling caps. added 2010-08-11 01:38:37 +03:00			`F6 "M0_A[0..12]" O L 5950 5150 60`
			`F7 "M1_A[0..12]" O L 5950 3050 60`
			`F8 "M0_DQ[0..15]" B L 5950 5050 60`
			`F9 "M0_UDQS" O L 5950 5400 60`
			`F10 "M0_LDM" O L 5950 5800 60`
			`F11 "M0_LDQS" O L 5950 5500 60`
			`F12 "M0_UDM" O L 5950 5700 60`
			`F13 "M0_RAS#" O L 5950 6400 60`
			`F14 "M0_WE#" O L 5950 6550 60`
			`F15 "M0_CKE" O L 5950 5950 60`
			`F16 "M0_CAS#" O L 5950 6300 60`
			`F17 "M1_CAS#" O L 5950 4250 60`
			`F18 "M1_CKE" O L 5950 3900 60`
			`F19 "M0_CS#" O L 5950 4900 60`
			`F20 "M1_CS#" O L 5950 2800 60`
			`F21 "M1_WE#" O L 5950 4500 60`
			`F22 "M1_RAS#" O L 5950 4350 60`
			`F23 "M1_UDM" O L 5950 3650 60`
			`F24 "M1_LDQS" O L 5950 3450 60`
			`F25 "M1_LDM" O L 5950 3750 60`
			`F26 "M1_UDQS" O L 5950 3350 60`
			`F27 "M1_DQ[0..15]" B L 5950 2950 60`
			`F28 "M1_BA[0..1]" O L 5950 3150 60`
			`F29 "M0_BA[0..1]" O L 5950 5250 60`
			`F30 "USBA_VM" B R 9300 5400 60`
			`F31 "USBA_VP" B R 9300 5300 60`
			`F32 "USBA_RCV" B R 9300 5200 60`
			`F33 "USBA_OE_N" B R 9300 5100 60`
			`F34 "USBA_SPD" B R 9300 5000 60`
			`F35 "ETH_CLK" B R 9300 7900 60`
			`F36 "ETH_RXC" B R 9300 6500 60`
			`F37 "ETH_TXC" B R 9300 7500 60`
			`F38 "ETH_TXD[0..3]" O R 9300 7600 60`
			`F39 "ETH_TXEN" B R 9300 7700 60`
			`F40 "ETH_TXER" B R 9300 7800 60`
			`F41 "ETH_RXER" B R 9300 7400 60`
			`F42 "ETH_RXDV" B R 9300 7300 60`
			`F43 "ETH_RXD[0..3]" I R 9300 7200 60`
			`F44 "ETH_RESET_N" B R 9300 6600 60`
			`F45 "ETH_MDIO" B R 9300 6900 60`
			`F46 "ETH_MDC" B R 9300 7000 60`
			`F47 "ETH_INT" B R 9300 6350 60`
SD connector attached to th S6 2010-08-11 02:09:38 +03:00			`F48 "SD_CLK" B R 9300 2900 60`
			`F49 "SD_CMD" B R 9300 3000 60`
			`F50 "SD_DAT[0..3]" B R 9300 3100 60`
Fixing USB connections 2010-08-11 05:25:32 +03:00			`F51 "ETH_CRS" I R 9300 6700 60`
			`F52 "ETH_COL" I R 9300 6800 60`
fix 2010-08-13 05:12:14 +03:00			`F53 "NF_D[0..7]" B R 9300 4050 60`
Ethernet-phy and USB connected to FPGA 2010-08-09 23:37:18 +03:00			`$EndSheet`
			`$Sheet`
			`S 10600 6250 1300 1800`
			`U 4C4320F3`
			`F0 "Ethernet Phy" 60`
			`F1 "eth_phy.sch" 60`
			`F2 "ETH_RXC" O L 10600 6500 60`
			`F3 "ETH_RST_N" I L 10600 6600 60`
			`F4 "ETH_CRS" O L 10600 6700 60`
			`F5 "ETH_COL" O L 10600 6800 60`
annotate 2010-08-10 05:55:50 +03:00			`F6 "ETH_MDIO" B L 10600 6900 60`
			`F7 "ETH_MDC" I L 10600 7000 60`
			`F8 "ETH_RXD[0..3]" O L 10600 7200 60`
			`F9 "ETH_RXDV" O L 10600 7300 60`
			`F10 "ETH_RXER" O L 10600 7400 60`
			`F11 "ETH_TXC" B L 10600 7500 60`
			`F12 "ETH_TXD[0..3]" I L 10600 7600 60`
			`F13 "ETH_TXEN" I L 10600 7700 60`
			`F14 "ETH_TXER" I L 10600 7800 60`
			`F15 "ETH_CLK" I L 10600 7900 60`
			`F16 "ETH_INT" O L 10600 6350 60`
Ethernet-phy and USB connected to FPGA 2010-08-09 23:37:18 +03:00			`$EndSheet`
initial import 2010-07-24 14:58:53 +03:00			`$Sheet`
USB and MICROSD footprints added 2010-08-09 01:54:09 +03:00			`S 10650 2700 1150 1850`
initial import 2010-07-24 14:58:53 +03:00			`U 4C4227FE`
			`F0 "Non volatile memories" 60`
			`F1 "NV_MEMORIES.sch" 60`
SD connector attached to th S6 2010-08-11 02:09:38 +03:00			`F2 "SD_CMD" I L 10650 3000 60`
			`F3 "SD_CLK" I L 10650 2900 60`
			`F4 "SD_DAT[0..3]" B L 10650 3100 60`
fix 2010-08-13 01:18:08 +03:00			`F5 "NF_D[0..7]" B L 10650 4050 60`
			`F6 "FWE_N" B L 10650 3450 60`
			`F7 "NF_ALE" B L 10650 3550 60`
			`F8 "NF_CLE" B L 10650 3650 60`
			`F9 "NF_WE_N" B L 10650 3750 60`
			`F10 "NF_CS1_N" B L 10650 3350 60`
			`F11 "NF_RE_N" B L 10650 3850 60`
			`F12 "NF_RNB" B L 10650 3950 60`
initial import 2010-07-24 14:58:53 +03:00			`$EndSheet`
			`$Sheet`
USB and MICROSD footprints added 2010-08-09 01:54:09 +03:00			`S 3600 2700 1100 4000`
initial import 2010-07-24 14:58:53 +03:00			`U 4C421DD3`
			`F0 "DDR Banks" 60`
			`F1 "DRAM.sch" 60`
USB and MICROSD footprints added 2010-08-09 01:54:09 +03:00			`F2 "M0_BA[0..1]" I R 4700 5250 60`
			`F3 "M1_BA[0..1]" I R 4700 3150 60`
			`F4 "M0_WE#" I R 4700 6550 60`
			`F5 "M0_RAS#" I R 4700 6400 60`
			`F6 "M1_RAS#" I R 4700 4350 60`
			`F7 "M1_WE#" I R 4700 4500 60`
			`F8 "M0_CAS#" I R 4700 6300 60`
			`F9 "M0_CKE" I R 4700 5950 60`
			`F10 "M0_CLK" I R 4700 6050 60`
			`F11 "M0_CLK#" I R 4700 6150 60`
			`F12 "M0_CS#" I R 4700 4900 60`
			`F13 "M1_CLK#" I R 4700 4100 60`
			`F14 "M1_CLK" I R 4700 4000 60`
			`F15 "M1_CKE" I R 4700 3900 60`
			`F16 "M1_CAS#" I R 4700 4250 60`
			`F17 "M0_DQ[0..15]" B R 4700 5050 60`
			`F18 "M0_UDM" I R 4700 5700 60`
			`F19 "M0_LDQS" I R 4700 5500 60`
			`F20 "M0_A[0..12]" I R 4700 5150 60`
			`F21 "M0_LDM" I R 4700 5800 60`
			`F22 "M0_UDQS" I R 4700 5400 60`
			`F23 "M1_UDQS" I R 4700 3350 60`
			`F24 "M1_LDM" I R 4700 3750 60`
			`F25 "M1_LDQS" I R 4700 3450 60`
			`F26 "M1_UDM" I R 4700 3650 60`
			`F27 "M1_CS#" I R 4700 2800 60`
			`F28 "M1_A[0..12]" I R 4700 3050 60`
			`F29 "M1_DQ[0..15]" B R 4700 2950 60`
initial import 2010-07-24 14:58:53 +03:00			`$EndSheet`
			`$EndSCHEMATC`