2010-10-12 19:12:31 +03:00
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EESchema Schematic File Version 2 date Sun 10 Oct 2010 06:23:22 PM COT
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2010-10-10 00:11:11 +03:00
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LIBS:power
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LIBS:r_pack2
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LIBS:v0402mhs03
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LIBS:usb-48204-0001
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LIBS:microsmd075f
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LIBS:mic2550
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LIBS:rj45-48025
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LIBS:xue-nv
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LIBS:xc6slx75fgg484
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LIBS:xc6slx45fgg484
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LIBS:micron_mobile_ddr
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LIBS:micron_ddr_512Mb
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LIBS:k8001
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LIBS:device
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LIBS:transistors
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LIBS:conn
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LIBS:linear
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LIBS:regul
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LIBS:74xx
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LIBS:cmos4000
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LIBS:adc-dac
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LIBS:memory
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LIBS:xilinx
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LIBS:special
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LIBS:microcontrollers
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LIBS:dsp
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LIBS:microchip
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LIBS:analog_switches
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LIBS:motorola
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LIBS:texas
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LIBS:intel
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LIBS:audio
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LIBS:interface
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LIBS:digital-audio
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LIBS:philips
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LIBS:display
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LIBS:cypress
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LIBS:siliconi
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LIBS:opto
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LIBS:atmel
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LIBS:contrib
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LIBS:valves
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LIBS:pasives-connectors
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LIBS:x25x64mb
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LIBS:attiny
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LIBS:PSU
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LIBS:tps793xx
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LIBS:reg102
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LIBS:mt9m033
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LIBS:m12-tu400a
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LIBS:xue-rnc-cache
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EELAYER 24 0
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EELAYER END
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$Descr A4 11700 8267
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Sheet 2 12
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Title ""
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2010-10-10 17:28:33 +03:00
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Date "10 oct 2010"
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2010-10-10 00:11:11 +03:00
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Rev ""
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Comp ""
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Comment1 ""
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Comment2 ""
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Comment3 ""
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Comment4 ""
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$EndDescr
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2010-10-12 19:12:31 +03:00
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Text Label 1650 1450 0 60 ~ 0
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FPGA_BANK0_IO_0
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Text Label 1650 1550 0 60 ~ 0
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FPGA_BANK0_IO_1
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Text Label 1650 1750 0 60 ~ 0
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FPGA_BANK0_IO_3
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Text Label 1650 1650 0 60 ~ 0
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FPGA_BANK0_IO_2
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Text Label 1650 2050 0 60 ~ 0
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FPGA_BANK0_IO_6
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Text Label 1650 2150 0 60 ~ 0
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FPGA_BANK0_IO_7
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Text Label 1650 1950 0 60 ~ 0
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FPGA_BANK0_IO_5
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Text Label 1650 1850 0 60 ~ 0
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FPGA_BANK0_IO_4
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Text Label 1650 2650 0 60 ~ 0
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FPGA_BANK0_IO_12
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Text Label 1650 2750 0 60 ~ 0
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FPGA_BANK0_IO_13
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Text Label 1650 2950 0 60 ~ 0
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FPGA_BANK0_IO_15
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Text Label 1650 2850 0 60 ~ 0
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FPGA_BANK0_IO_14
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Text Label 1650 2450 0 60 ~ 0
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FPGA_BANK0_IO_10
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Text Label 1650 2550 0 60 ~ 0
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FPGA_BANK0_IO_11
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Text Label 1650 2350 0 60 ~ 0
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FPGA_BANK0_IO_9
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Text Label 1650 2250 0 60 ~ 0
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FPGA_BANK0_IO_8
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Entry Wire Line
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2550 1450 2650 1550
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Entry Wire Line
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2550 1650 2650 1750
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Entry Wire Line
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2550 1550 2650 1650
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Entry Wire Line
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2550 1750 2650 1850
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Entry Wire Line
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2550 1850 2650 1950
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Entry Wire Line
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2550 1950 2650 2050
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Entry Wire Line
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2550 2050 2650 2150
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Entry Wire Line
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2550 2150 2650 2250
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Entry Wire Line
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2550 2250 2650 2350
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Entry Wire Line
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2550 2950 2650 3050
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Entry Wire Line
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2550 2850 2650 2950
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Entry Wire Line
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2550 2750 2650 2850
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Entry Wire Line
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2550 2550 2650 2650
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Entry Wire Line
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2550 2450 2650 2550
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Entry Wire Line
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2550 2350 2650 2450
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Entry Wire Line
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2550 2650 2650 2750
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Text HLabel 3550 1300 2 60 BiDi ~ 0
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FPGA_BANK0_IO_[0..64]
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Text Label 1650 3050 0 60 ~ 0
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FPGA_BANK0_IO_16
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Text Label 1650 3150 0 60 ~ 0
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FPGA_BANK0_IO_17
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Text Label 1650 3350 0 60 ~ 0
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FPGA_BANK0_IO_19
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Text Label 1650 3250 0 60 ~ 0
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FPGA_BANK0_IO_18
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Text Label 1650 3650 0 60 ~ 0
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FPGA_BANK0_IO_22
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Text Label 1650 3750 0 60 ~ 0
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FPGA_BANK0_IO_23
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Text Label 1650 3550 0 60 ~ 0
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FPGA_BANK0_IO_21
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Text Label 1650 3450 0 60 ~ 0
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FPGA_BANK0_IO_20
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Text Label 1650 4250 0 60 ~ 0
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FPGA_BANK0_IO_28
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Text Label 1650 4350 0 60 ~ 0
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FPGA_BANK0_IO_29
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Text Label 1650 4550 0 60 ~ 0
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FPGA_BANK0_IO_31
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Text Label 1650 4450 0 60 ~ 0
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FPGA_BANK0_IO_30
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Text Label 1650 4050 0 60 ~ 0
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FPGA_BANK0_IO_26
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Text Label 1650 4150 0 60 ~ 0
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FPGA_BANK0_IO_27
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Text Label 1650 3950 0 60 ~ 0
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FPGA_BANK0_IO_25
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Text Label 1650 3850 0 60 ~ 0
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FPGA_BANK0_IO_24
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Text Label 1650 4650 0 60 ~ 0
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FPGA_BANK0_IO_32
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Text Label 1650 4750 0 60 ~ 0
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FPGA_BANK0_IO_33
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Entry Wire Line
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2850 5150 2950 5050
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Entry Wire Line
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2850 5050 2950 4950
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Text Label 2950 4950 0 60 ~ 0
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FPGA_BANK0_IO_35
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Text Label 2950 5050 0 60 ~ 0
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FPGA_BANK0_IO_34
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Text Label 2950 4850 0 60 ~ 0
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FPGA_BANK0_IO_36
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Text Label 2950 4750 0 60 ~ 0
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FPGA_BANK0_IO_37
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Entry Wire Line
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2850 4850 2950 4750
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Entry Wire Line
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2850 4950 2950 4850
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Entry Wire Line
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2850 4750 2950 4650
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Entry Wire Line
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2850 4650 2950 4550
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Text Label 2950 4550 0 60 ~ 0
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FPGA_BANK0_IO_39
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Text Label 2950 4650 0 60 ~ 0
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FPGA_BANK0_IO_38
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Text Label 2950 4450 0 60 ~ 0
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FPGA_BANK0_IO_40
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Text Label 2950 4350 0 60 ~ 0
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FPGA_BANK0_IO_41
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Entry Wire Line
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2850 4450 2950 4350
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Entry Wire Line
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2850 4550 2950 4450
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Entry Wire Line
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2850 4350 2950 4250
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Entry Wire Line
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2850 4250 2950 4150
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Text Label 2950 4150 0 60 ~ 0
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FPGA_BANK0_IO_43
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Text Label 2950 4250 0 60 ~ 0
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FPGA_BANK0_IO_42
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Text Label 2950 4050 0 60 ~ 0
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FPGA_BANK0_IO_44
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Text Label 2950 3950 0 60 ~ 0
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FPGA_BANK0_IO_45
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Entry Wire Line
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2850 4050 2950 3950
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Entry Wire Line
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2850 4150 2950 4050
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Entry Wire Line
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2850 3950 2950 3850
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Entry Wire Line
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2850 3850 2950 3750
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Text Label 2950 3750 0 60 ~ 0
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FPGA_BANK0_IO_47
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Text Label 2950 3850 0 60 ~ 0
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FPGA_BANK0_IO_46
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Text Label 2950 3650 0 60 ~ 0
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FPGA_BANK0_IO_48
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Text Label 2950 3550 0 60 ~ 0
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FPGA_BANK0_IO_49
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Entry Wire Line
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2850 3650 2950 3550
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Entry Wire Line
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2850 3750 2950 3650
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Entry Wire Line
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2850 3550 2950 3450
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Entry Wire Line
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2850 3450 2950 3350
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Text Label 2950 3350 0 60 ~ 0
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FPGA_BANK0_IO_51
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Text Label 2950 3450 0 60 ~ 0
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FPGA_BANK0_IO_50
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Text Label 2950 3250 0 60 ~ 0
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FPGA_BANK0_IO_52
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Text Label 2950 3150 0 60 ~ 0
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FPGA_BANK0_IO_53
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Entry Wire Line
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2850 3250 2950 3150
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Entry Wire Line
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2850 3350 2950 3250
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Entry Wire Line
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2850 3150 2950 3050
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Entry Wire Line
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2850 3050 2950 2950
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Text Label 2950 2950 0 60 ~ 0
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FPGA_BANK0_IO_55
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Text Label 2950 3050 0 60 ~ 0
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FPGA_BANK0_IO_54
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Text Label 2950 2250 0 60 ~ 0
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FPGA_BANK0_IO_62
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Text Label 2950 2150 0 60 ~ 0
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FPGA_BANK0_IO_63
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Text Label 2950 2350 0 60 ~ 0
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FPGA_BANK0_IO_61
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Text Label 2950 2450 0 60 ~ 0
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FPGA_BANK0_IO_60
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Text Label 2950 2050 0 60 ~ 0
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FPGA_BANK0_IO_64
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Text Label 2950 2850 0 60 ~ 0
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FPGA_BANK0_IO_56
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Text Label 2950 2750 0 60 ~ 0
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FPGA_BANK0_IO_57
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Text Label 2950 2550 0 60 ~ 0
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FPGA_BANK0_IO_59
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Text Label 2950 2650 0 60 ~ 0
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FPGA_BANK0_IO_58
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Entry Wire Line
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2550 4250 2650 4350
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Entry Wire Line
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2550 3950 2650 4050
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Entry Wire Line
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2550 4050 2650 4150
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Entry Wire Line
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2550 4150 2650 4250
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Entry Wire Line
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2550 4350 2650 4450
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Entry Wire Line
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2550 4450 2650 4550
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Entry Wire Line
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2550 4550 2650 4650
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Entry Wire Line
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2550 3850 2650 3950
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Entry Wire Line
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2550 3750 2650 3850
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Entry Wire Line
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2550 3650 2650 3750
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Entry Wire Line
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2550 3550 2650 3650
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Entry Wire Line
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2550 3450 2650 3550
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Entry Wire Line
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2550 3350 2650 3450
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Entry Wire Line
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2550 3150 2650 3250
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Entry Wire Line
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2550 3250 2650 3350
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Entry Wire Line
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2550 3050 2650 3150
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Entry Wire Line
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2550 4750 2650 4850
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Entry Wire Line
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2550 4650 2650 4750
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Text Label 1650 5050 0 60 ~ 0
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FPGA_BANK0_IO_36
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Text Label 1650 4850 0 60 ~ 0
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FPGA_BANK0_IO_34
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Text Label 1650 4950 0 60 ~ 0
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FPGA_BANK0_IO_35
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Entry Wire Line
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2550 4950 2650 5050
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Entry Wire Line
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2550 5050 2650 5150
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Entry Wire Line
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2550 4850 2650 4950
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Wire Bus Line
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2650 5250 2850 5250
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Wire Bus Line
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2650 1550 2650 5250
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Wire Wire Line
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1650 4950 2550 4950
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Wire Wire Line
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2550 4750 1650 4750
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Wire Wire Line
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3800 2050 2950 2050
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Wire Wire Line
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3800 2250 2950 2250
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Wire Wire Line
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3800 2150 2950 2150
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Wire Wire Line
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3800 2350 2950 2350
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Wire Wire Line
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3800 2450 2950 2450
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Wire Wire Line
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3800 3250 2950 3250
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Wire Wire Line
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3800 3150 2950 3150
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Wire Wire Line
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3800 2950 2950 2950
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Wire Wire Line
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3800 3050 2950 3050
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Wire Wire Line
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2550 3050 1650 3050
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Wire Wire Line
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1650 4650 2550 4650
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Wire Wire Line
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2550 1450 1650 1450
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Wire Wire Line
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2550 1550 1650 1550
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Wire Wire Line
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2550 1750 1650 1750
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Wire Wire Line
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2550 1650 1650 1650
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Wire Wire Line
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2550 2050 1650 2050
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Wire Wire Line
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2550 2150 1650 2150
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Wire Wire Line
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2550 1950 1650 1950
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Wire Wire Line
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2550 1850 1650 1850
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Wire Wire Line
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2550 2650 1650 2650
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Wire Wire Line
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2550 2750 1650 2750
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Wire Wire Line
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2550 2950 1650 2950
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Wire Wire Line
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2550 2850 1650 2850
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Wire Wire Line
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2550 2450 1650 2450
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Wire Wire Line
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2550 2550 1650 2550
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Wire Wire Line
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2550 2350 1650 2350
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Wire Wire Line
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|
|
2550 2250 1650 2250
|
|
|
|
Wire Wire Line
|
|
|
|
1650 4550 2550 4550
|
|
|
|
Wire Wire Line
|
|
|
|
1650 4350 2550 4350
|
|
|
|
Wire Wire Line
|
|
|
|
1650 4450 2550 4450
|
|
|
|
Wire Wire Line
|
|
|
|
1650 4050 2550 4050
|
|
|
|
Wire Wire Line
|
|
|
|
1650 3950 2550 3950
|
|
|
|
Wire Wire Line
|
|
|
|
1650 4150 2550 4150
|
|
|
|
Wire Wire Line
|
|
|
|
1650 4250 2550 4250
|
|
|
|
Wire Wire Line
|
|
|
|
1650 3450 2550 3450
|
|
|
|
Wire Wire Line
|
|
|
|
1650 3350 2550 3350
|
|
|
|
Wire Wire Line
|
|
|
|
1650 3150 2550 3150
|
|
|
|
Wire Wire Line
|
|
|
|
1650 3250 2550 3250
|
|
|
|
Wire Wire Line
|
|
|
|
1650 3650 2550 3650
|
|
|
|
Wire Wire Line
|
|
|
|
1650 3550 2550 3550
|
|
|
|
Wire Wire Line
|
|
|
|
1650 3750 2550 3750
|
|
|
|
Wire Wire Line
|
|
|
|
1650 3850 2550 3850
|
|
|
|
Wire Wire Line
|
|
|
|
3800 4950 2950 4950
|
|
|
|
Wire Wire Line
|
|
|
|
3800 5050 2950 5050
|
|
|
|
Wire Wire Line
|
|
|
|
3800 4850 2950 4850
|
|
|
|
Wire Wire Line
|
|
|
|
3800 4750 2950 4750
|
|
|
|
Wire Wire Line
|
|
|
|
3800 4550 2950 4550
|
|
|
|
Wire Wire Line
|
|
|
|
3800 4650 2950 4650
|
|
|
|
Wire Wire Line
|
|
|
|
3800 4450 2950 4450
|
|
|
|
Wire Wire Line
|
|
|
|
3800 4350 2950 4350
|
|
|
|
Wire Wire Line
|
|
|
|
3800 4150 2950 4150
|
|
|
|
Wire Wire Line
|
|
|
|
3800 4250 2950 4250
|
|
|
|
Wire Wire Line
|
|
|
|
3800 4050 2950 4050
|
|
|
|
Wire Wire Line
|
|
|
|
3800 3950 2950 3950
|
|
|
|
Wire Wire Line
|
|
|
|
3800 3750 2950 3750
|
|
|
|
Wire Wire Line
|
|
|
|
3800 3850 2950 3850
|
|
|
|
Wire Wire Line
|
|
|
|
3800 3650 2950 3650
|
|
|
|
Wire Wire Line
|
|
|
|
3800 3550 2950 3550
|
|
|
|
Wire Wire Line
|
|
|
|
3800 3350 2950 3350
|
|
|
|
Wire Wire Line
|
|
|
|
3800 3450 2950 3450
|
|
|
|
Wire Wire Line
|
|
|
|
3800 2850 2950 2850
|
|
|
|
Wire Wire Line
|
|
|
|
3800 2750 2950 2750
|
|
|
|
Wire Wire Line
|
|
|
|
3800 2550 2950 2550
|
|
|
|
Wire Wire Line
|
|
|
|
3800 2650 2950 2650
|
|
|
|
Wire Wire Line
|
|
|
|
2550 4850 1650 4850
|
|
|
|
Wire Wire Line
|
|
|
|
1650 5050 2550 5050
|
|
|
|
Wire Bus Line
|
|
|
|
2850 1300 2850 5250
|
|
|
|
Wire Bus Line
|
|
|
|
2850 1300 3550 1300
|
|
|
|
Entry Wire Line
|
|
|
|
2850 2950 2950 2850
|
|
|
|
Entry Wire Line
|
|
|
|
2850 2850 2950 2750
|
|
|
|
Entry Wire Line
|
|
|
|
2850 2750 2950 2650
|
|
|
|
Entry Wire Line
|
|
|
|
2850 2650 2950 2550
|
|
|
|
Entry Wire Line
|
|
|
|
2850 2550 2950 2450
|
|
|
|
Entry Wire Line
|
|
|
|
2850 2450 2950 2350
|
|
|
|
Entry Wire Line
|
|
|
|
2850 2350 2950 2250
|
|
|
|
Entry Wire Line
|
|
|
|
2850 2250 2950 2150
|
|
|
|
Entry Wire Line
|
|
|
|
2850 2150 2950 2050
|
2010-10-10 00:11:11 +03:00
|
|
|
$Comp
|
2010-10-10 17:28:33 +03:00
|
|
|
L CONN_20X2 P2
|
2010-10-10 00:11:11 +03:00
|
|
|
U 1 1 4CB0D9BF
|
|
|
|
P 6200 1900
|
2010-10-10 17:28:33 +03:00
|
|
|
F 0 "P2" H 6200 2950 60 0000 C CNN
|
2010-10-10 00:11:11 +03:00
|
|
|
F 1 "CONN_20X2" V 6200 1900 50 0000 C CNN
|
2010-10-10 17:28:33 +03:00
|
|
|
F 2 "header20x2_smd_100mil" H 6140 3010 60 0001 C CNN
|
2010-10-10 00:11:11 +03:00
|
|
|
1 6200 1900
|
|
|
|
1 0 0 -1
|
|
|
|
$EndComp
|
|
|
|
$EndSCHEMATC
|